Design of Low-Cost Memory-Based Security Primitives and Techniques for High-Volume Products

  • Authors:
    Domenic Forte (Univ. of Florida), Mark M. Tehranipoor (Univ. of Florida), Tauhid Rahman (Univ. of Florida), Zimu Guo (Univ. of Florida)
    Publication ID:
    Publication Type:
    Annual Review
    Received Date:
    Last Edit Date:
    2648.001 (University of Florida)


In this project, new metrics and algorithms that exploit existing resources to cover multiple primitives simultaneously are developed. To be more specific, SRAM, DRAM, and Flash are used to create low-cost hardware security primitives: memory-based PUFs (M-PUFs), memory-based TRNGs (here called M-TRNGs), and memory for counterfeit IC detection (M-AC). This publication contains a summary of the progress thus far in this project followed by a review of research and results in year 3, particularly presenting (1) algorithms, metrics, and silicon results for improved M-AC based recycled SoC detection based on statistical inference of SRAM. Results are improved compared to year 2 and are less dependent on initialization parameters; (2) framework for fake Flash detection (FFD) and results. This framework models the flash memory aging by investigating the floating gate transistor failures. These failures are characterized by partially programming a page. The capabilities of our framework can be categorized into recycled flash memory detection and usage estimation. The recycled flash memory determination capability is crucial in critical applications since it distinguishes low-quality from high-quality flash memory chips. The usage estimation capabilities allow non-critical applications to monitor the usage of the flash memory. We also generate unique IDs using FFD; (3) Preliminary investigation and results for PUF based on DRAM latency. Such a PUF does not have the limitations of other DRAM PUFs which take long time (tens of seconds to generate a signature). Naive methods do not perform well, but by taking advantage of physical location (neighborhood analysis), DRAM latency PUF becomes more promising. For the remainder of the project, we will continue to investigate DRAM latency for PUF, TRNG, and anti-recycling; and (4) Finally, we summarize all the advantages/disadvantages of the project so far in terms of cost, performance, and practical needs (database, enrollment, etc.).

Past Events

  Event Summary
13–14 July 2017
Trustworthy and Secure Semiconductors and Systems (T3S) Review
Thursday, July 13, 2017, 8 a.m. — Friday, July 14, 2017, 6:30 p.m. ET
Norwood, MA, United States

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