Low Barrier Nanomagnets as p-bits for Invertible Logic

  • Authors:
    Rafatul Faria (Purdue), Supriyo Datta (Purdue), Kerem Yunus Camsari (Purdue)
    Publication ID:
    P092094
    Publication Type:
    Poster
    Received Date:
    4-Sep-2017
    Last Edit Date:
    5-Sep-2017
    Research:
    2399.002 (SUNY Polytechnic Institute)

Abstract

Conventional logic and memory devices are built out of stable deterministic units such as standard MOS transistors, or nanomagnets with energy barriers in excess of ∼40-60 kT. By contrast, we argue that unstable, stochastic units can be interconnected to create robust correlations that can be used to solve a wide variety of problems that not only includes optimization and inference but also precise Boolean logic. We will illustrate some of these functionalities using a simple generic model for pbits which agree well with those obtained for low barrier magnets (∼ 1 kT) from the stochastic Landau-Lifshitz-Gilbert (sLLG) equation. Note, however, that p-bits need not be magnet-based: any tunable random bit generator should be suitable. We will present a striking example of a 32-bit adder implemented using an interconnected network of p-bits. Initially when the connections are weak relative to the noise, the sum bits (S) fluctuate in an uncorrelated manner. But once the connections are turned on, they overcome the noise and the magnets get precisely correlated to converge on THE one correct answer out of 233 (∼ 8 billion) possibilities! Remarkably the adder is invertible as well. When the output (S) is clamped to a fixed number, the inputs (A) and (B) fluctuate in a correlated manner to make A+B=S. This ability of a system to implement the inverse function is a rare feature with far-reaching possibilities. For example, we have shown that a 4-bit multiplier acting in the inverse mode performs integer factorization, suggesting that probabilistic computers based on robust room temperature p-bits could provide practically useful solutions to many challenging problems by rapidly sampling the phase space in hardware.

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10–12 September 2017
SRC
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