3D IC Thermal Management Based on TSV Placement Optimization and Novel Materials

  • Authors:
    Zongqing Ren (UC/Irvine), Ayed S. Alqahtani (UC/Irvine), Nader Bagherzadeh (UC/Irvine), Jaeho Lee (UC/Irvine)
    Publication ID:
    P092618
    Publication Type:
    Poster
    Received Date:
    13-Oct-2017
    Last Edit Date:
    16-Oct-2017
    Research:
    2712.016 (University of California/Irvine)

Abstract

Vertically stack three dimension integrated circuits (3D ICs) has emerged as a viable solution for high-performance computing as IC technology feature sizes decrease. One of the 3D ICs critical issues is thermal management. Hence, the reduction of the adverse effects of temperature elevation of 3D ICs requires a thorough investigation of TTSVs (Thermal Through Silicon Via). Current researches involving TSV designs have focused on providing solutions either from an electrical or thermal perspective.

The focus of our work is to study the impact of including thermal TSV (TTSV) early in the system design process and provide effective thermal management solutions for 3D ICs by addressing the electrical workload, optimizing TTSV design parameters, and considering novel TTSV materials.

Past Events

  Event Summary
17–19 October 2017
GRC
GRC
Texas Analog Center of Excellence and Analog/Mixed-Signal Circuits, Systems and Devices Review
Tuesday, Oct. 17, 2017, 8 a.m. — Thursday, Oct. 19, 2017, noon CT
Richardson, TX, United States

4819 Emperor Blvd, Suite 300 Durham, NC 27703 Voice: (919) 941-9400 Fax: (919) 941-9450

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