Report on Matlab/Simulink Behavioral Models for the Proposed Architecture

  • Authors:
    Arindam Sanyal (Univ. at Buffalo), Mohammadhadi Danesh (Univ. at Buffalo), Sanjeev Tannirkulam Chandrasekaran (Univ. at Buffalo)
    Publication ID:
    Publication Type:
    Deliverable Report
    Received Date:
    Last Edit Date:
    2712.020 (University at Buffalo - SUNY)


This report summarizes the result of architectural study using behavioral models for the proposed continuous-time second-order VCO based delta-sigma ADC. The ADC has been modeled using Matlab Simulink and includes the effects of thermal noise, DAC mismatch, intersymbol interference (ISI) error and clock jitter. The architectural study clearly shows that highly digital second-order delta-sigma ADC can be built using only VCOs as integrators. The behavioral model also shows that the proposed architecture has good insensitivity to static and dynamic errors in the DAC. The behavioral model has been used to design prototype ADC in 65nm CMOS process.

4819 Emperor Blvd, Suite 300 Durham, NC 27703 Voice: (919) 941-9400 Fax: (919) 941-9450

Important Information for the SRC website. This site uses cookies to store information on your computer. By continuing to use our site, you consent to our cookies. If you are not happy with the use of these cookies, please review our Cookie Policy to learn how they can be disabled. By disabling cookies, some features of the site will not work.