Report on Matlab/Simulink Behavioral Models for the Proposed Architecture

  • Authors:
    Arindam Sanyal (Univ. at Buffalo), Mohammadhadi Danesh (Univ. at Buffalo), Sanjeev Tannirkulam Chandrasekaran (Univ. at Buffalo)
    Publication ID:
    P092919
    Publication Type:
    Deliverable Report
    Received Date:
    13-Dec-2017
    Last Edit Date:
    14-Dec-2017
    Research:
    2712.020 (University at Buffalo - SUNY)

Abstract

This report summarizes the result of architectural study using behavioral models for the proposed continuous-time second-order VCO based delta-sigma ADC. The ADC has been modeled using Matlab Simulink and includes the effects of thermal noise, DAC mismatch, intersymbol interference (ISI) error and clock jitter. The architectural study clearly shows that highly digital second-order delta-sigma ADC can be built using only VCOs as integrators. The behavioral model also shows that the proposed architecture has good insensitivity to static and dynamic errors in the DAC. The behavioral model has been used to design prototype ADC in 65nm CMOS process.

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