Report on a Fast, Parallelized, Test Stimulus Generator for Detecting Design Bugs (scalable from pre to post-silicon) Based on Directed Stochastic Search Coupled with Gradient Descent Techniques for Rapid Convergence

  • Authors:
    Abhijit Chatterjee (Georgia Tech), Barry Muldrey (Georgia Tech)
    Publication ID:
    P092954
    Publication Type:
    Deliverable Report
    Received Date:
    21-Dec-2017
    Last Edit Date:
    18-Jan-2018
    Research:
    2712.005 (Georgia Institute of Technology)

Research Report Highlight

TxACE researchers at GaTech investigate the use of reinforcement learning algorithms to speed up test stimulus design.

Abstract

The contemporary top-down design of analog and mixed-signal systems requires that low-level design descriptions be continually validated against higher level specifications. As the lower-level (transistor-level, silicon) implementations become available, their behavior is vetted against that of their abstraction models. Increased circuit complexity and narrow margins can cause unforeseen or overlooked low-level nonidealities to violate high-level specifications. Identification of such specification violations must occur as early in the design process as possible to enable design correction in time to meet delivery constraints. In systems with even moderate numbers of inputs and depth of memory, the operational space of the system becomes intractably large, ruling out an exhaustive search for design bugs. Various techniques have been proposed in the literature for efficient exploration of systems' operational space in search of design anomalies. In this work, we describe a novel procedure utilizing contemporary reinforcement-learning techniques for analog and mixed-signal design validation. We present our formulation of the validation problem and explain how it integrates with deep Q-learning and deep deterministic policy gradient paradigms. We present selected experimental results and discuss the challenges posed by various use cases.

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