Digital PLL Based CT Delta-Sigma VCO ADC

  • Authors:
    Mohammadhadi Danesh (Univ. at Buffalo), Sanjeev Tannirkulam Chandrasekaran (Univ. at Buffalo), Arindam Sanyal (Univ. at Buffalo), Akshay Jayaraj (Univ. at Buffalo)
    Publication ID:
    P093726
    Publication Type:
    Paper
    Received Date:
    20-Jun-2018
    Last Edit Date:
    5-Feb-2019
    Research:
    2712.020 (University at Buffalo - SUNY)

Abstract

A continuous-time (CT) second-order Delta-Sigma analog-to-digital converter (ADC) is presented in this paper. The proposed ADC is based on a novel architecture and uses current starved ring oscillators as integrators to achieve second-order noise shaping. The proposed architecture does not require excess loop delay compensation or nonlinearity calibration. Static element mismatch in the multi-bit current digital-to-analog converter (DAC) is high-pass shaped by intrinsic data weighted averaging. Detailed analysis and insights on the various trade-offs involved in the design of the proposed ADC are presented in this work. A prototype ADC is implemented in 65nm CMOS and achieves 64.2dB SNDR at a bandwidth of 2.5MHz and a schreier FoM of 158.2dB. The ADC operates at 205MHz and consumes 1mW of power. The measured power supply rejection ratio (PSRR) is 56.2dB.

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