0.43nJ, 1.2pJ/step Second-Order Delta-Sigma Current-to-Digital Converter for IOT

  • Authors:
    Mohammadhadi Danesh (Univ. at Buffalo), Akshay Jayarj (Univ. at Buffalo), Sanjeev Tannirkulam Chandrasekaran (Univ. at Buffalo), Arindam Sanyal (Univ. at Buffalo)
    Publication ID:
    P093727
    Publication Type:
    Paper
    Received Date:
    20-Jun-2018
    Last Edit Date:
    5-Feb-2019
    Research:
    2712.020 (University at Buffalo - SUNY)

Abstract

A second-order Delta\Sigma current-to-digital converter (CDC) for IoT sensing applications is presented in this paper. The proposed CDC uses pseudo-differential current-starved ring oscillators as phase domain integrators. A negative feedback loop relaxes input ring oscillator nonlinearity. The proposed architecture does not require excess loop delay compensation or nonlinearity calibration. Digital differentiation using XOR implements an intrinsic first-order high-pass shaping of static element mismatch in the current steering digital-to-analog converter. A prototype CDC in 65nm CMOS process achieves 62dB dynamic range at 0.48pJ/conversion-step and has 20X better energy-efficiency than state-of-the-art.

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