Notre Dame researchers Mike Niemier and Sharon Hu have begun architectural-level benchmarking using data from Nanoelectronics Research Initiative benchmarking efforts to project how low-voltage steep-slope devices could ultimately impact the performance of a parallel benchmark suite (PARSEC) obtained by core scaling. For this work, they also leverage architectural models developed by Sankaralingam (University of Wisconsin) and Burger (Microsoft Research) that consider how technology, processor core design, and application models can impact core scaling.

Preliminary analysis suggests that some TFET-centric cores could deliver the desired chip-level speedup relative to the 45 nm technology node—at least for highly parallelizable benchmarks (representative of server workloads, etc.) Notably, assuming a graphene nanoribbon tunnel field-effect transistor (GNR TFET), the geometric mean of the speedups for Blackscholes through x264 is 9.12. (A value of 8 is sought as the 15 nm technology node is three generations removed from the 45 nm technology node.) For said benchmarks, the average chip-level power is just 31 W. Also, when considering symmetric multi-core chips comprised of GNR TFETs or InAs homojunction TFETs, for all benchmarks, “dark silicon” does not exist. Area and/or performance gains limit additional speedup, not power.