International Research Effort for Interconnect and Packaging to Slash Chip Footprint by 10X, will be Launched at Georgia Tech

SRC and State of Georgia announce $2.5M collaboration to fund university research at Georgia Tech, Harvard, UT-Austin, Iowa State and Singapore's Nanyang Technological University

Jan 26, 2009

RESEARCH TRIANGLE PARK, N.C. and ATLANTA - Semiconductor Research Corporation (SRC), the world's leading university-based research consortium for semiconductors and related technologies, today joined with Georgia Tech to announce a $2.5 million collaboration among academia, industry and government that will create the Interconnect and Packaging Center (IPC), based at Georgia Tech. Results from the joint research are expected to enable a reduction in the footprint of chips by a revolutionary factor of 10 while both decreasing power consumption and increasing performance.

The cooperative work of the center's participants is aimed at two objectives: creation of leading-edge technologies that connect billions of transistors on a chip, called interconnects, as well as improved ability of different chips to communicate with each other through enhanced packaging. Smaller, more powerful chips could be gained from such advancements.

"Transistors have made enormous progress in speed, performance, and miniaturization, which places greater demand on the electrical connections between transistors, and between individual chips. The interconnect and packaging challenges are greater today than ever," said Dr. Paul Kohl, director for the IPC. "Georgia Tech has been a leader in creating new interconnect and packaging technologies for integrated circuits and we're very pleased to partner with SRC in launching the IPC."

To facilitate huge computing gains, about half of the IPC research will focus on new 3D technology. 3D can provide the semiconductor industry with viable options for stacking multiple chips vertically at room temperature while maintaining millions of inter-die electrical connections.

"The 3D approach to packaging is one of the most promising options for improving functionality and performance to help ensure the continued success of the semiconductor industry," according to Dr. Scott List, director of Interconnect and Packaging Sciences for SRC-GRC, an SRC entity dedicated to extending the future of CMOS. "2009 is clearly a very difficult time for the industry but continued sharing of research dollars provides a strong prescription for a brighter future."

The Interconnect and Packaging Center begins immediate annual funding of $820,000 across its eight selected programs at Georgia Tech, Harvard, The University of Texas at Austin, Iowa State University and Nanyang Technological University (NTU). The international participation from Singapore's NTU marks a growing trend toward acceleration of progress through integration of the best global research.

SRC is providing $500,000 per year to IPC for three years. The State of Georgia is providing $320,000 for each of three years. The IPC will be based in the new Marcus Nanotechnology Building at Georgia Tech.

Per its charter, SRC will continue to take a lead role in collaborating on enhancements brought about by academic research associated with semiconductor design and manufacturing.

Global Research Collaboration (GRC) is one of three research program entities of SRC. Celebrating 27 years of collaborative research for the semiconductor industry, SRC defines industry needs, invests in and manages the research that gives its members a competitive advantage in the dynamic global marketplace. Awarded the National Medal of Technology, America's highest recognition for contributions to technology, SRC expands the industry knowledge base and attracts premier students to help innovate and transfer semiconductor technology to the commercial industry. For more information, visit

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