Semiconductor Research Corporation and Georgia Tech Boost Off-chip Bandwidth While Driving Down Energy Per Bit

Gains in Off-chip Interconnect to Enable Continued Improvements for Chip Scaling, Packaging, System Performance

Aug 17, 2010

RESEARCH TRIANGLE PARK, N.C. Semiconductor Research Corporation (SRC), the world's leading university-research consortium for semiconductors and related technologies, and researchers from Georgia Tech today announced two advancements proven to meet key challenges facing the industry with respect to off-chip interconnect solutions. The results address both the urgent need for greater off-chip bandwidth and reduced power per bit and promise to enable continued improvements for system performance.

Challenges Facing Higher Frequencies

On-chip computing continues to improve with scaling, but that doesn’t help off-chip communications. In fact, many on-chip computing advancements in recent years, including multicore processors, have greatly increased the demand for off-chip bandwidth to memory. As a result, system performance will slow unless off-chip bandwidth also rises.

Off-chip interconnect is considered a key enabler for continued performance scaling. However, the power dedicated to off-chip interconnect competes with the rest of the system for use of the available energy. This presents a challenge, as off-chip electrical communications need to simultaneously move to higher frequency per pin -- while also demanding less energy per bit of information. Typically, moving to higher frequency requires more energy per bit.

“Off-chip connectivity is both critical and essential for continued advancement of systems. However, most of the off-chip infrastructure used today -- chip substrates, printed circuit boards, and backplanes -- are unsuitable for these high frequencies because there are signal distortions and losses,” said Dr. Paul Kohl, director of the SRC-FCRP Interconnect Focus Center at Georgia Tech and lead researcher at Georgia Tech for several SRC-funded projects.

How to Solve the Problem

The first of the two advancements announced by SRC-FCRP and Georgia Tech—in collaboration with University of Florida professor Rizwan Bashirullah—provides for significant reduction in energy loss per bit in off-chip pathways. By using air as the dielectric material for substrate or board-level interconnect, signal distortions, losses and power consumption can all be greatly reduced. To create these structures with air dielectrics, new processes and sacrificial materials are used on organic boards. Related research involves differential pair conductors and multi-layer structures, where two or more layers of air-clad interconnect can be fabricated to further reduce energy loss.

Among the benefits from the multilayer stacking is that the number of off-chip bytes per on-chip floating point operation will drop. This means that on-chip calculations and access to memory will become more plentiful, compared to the traditional means for connecting to off-chip memory.

“Research in packaging is not as forward looking as in chips and tends to be incremental in nature. Particularly in view of the industry’s shortage of affordable solutions, these new results should be highly beneficial for our semiconductor industries,” said Betsy Weitzman, SRC executive vice president and executive director of the Focus Center Research Program (FCRP) funding the work on bandwidth.

The second advancement is the actual connection between the chip and substrate. Both the chip and the substrate use copper wiring. The weak link between them is the solder, which is the only non-copper element in the pathway. Solders are mechanically brittle and limit both the density and performance of flip-chip connections between chips and boards. Georgia Tech researchers are replacing solder with all-copper connections, which are made into non-spherical structures, such as shielded, co-axial or other shapes that enable higher densities and performance than current solder materials.

Not only does this approach support continued system performance improvements, but also provides an environmental improvement by creating a smaller chemical footprint during fabrication.

“These results reflect multi-disciplinary improvement where materials and chemical advances are brought together with electrical design and modeling achievements. They help to create significant system-level progress that should enable further system performance improvements,” said Dr. Scott List, director of Interconnect and Packaging Sciences within the SRC Global Research Consortium that is funding work to improve the interconnectivity.

The aim of the combined effort from SRC and Georgia Tech is to provide the industry with low-cost options for forming high-value structures. Among the key beneficiaries of the interconnect results are chipmakers, packaging houses and equipment manufacturers.

More details about the research can be found at

About SRC

Celebrating 28 years of collaborative research for the semiconductor industry, SRC defines industry needs, invests in and manages the research that gives its members a competitive advantage in the dynamic global marketplace. Awarded the National Medal of Technology, America’s highest recognition for contributions to technology, SRC expands the industry knowledge base and attracts premier students to help innovate and transfer semiconductor technology to the commercial industry. For more information, visit


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