Ultra-large-scale inte-grated circuits contain close to one hundred million transistors per square millimeter. More than 30 miles of interconnect wires run on each chip over ten or more levels of dielectrics to deliver electrical data and clock signals for high-throughput information processing. With the logic gate latency including wiring de-lay approaching one picosecond at the 10-nm technology node, interconnect scaling in future technology nodes will result in an unacceptable increase in resistance and inter-line capacitance, making interconnect latency the key performance bottleneck instead of front-end transistors. Both high-performance and ul-tra-low power modes of computation based on dynamic voltage frequency scaling (DVFS) will be adversely affected by rising interconnect resistance-capacitance (RC) issues. Additionally, the interconnect bottle-neck, which limits the data bandwidth, extends beyond the chip and is exacerbated as the volume of data to be gathered, processed, and analyzed grows super-exponentially. Processing and analyzing such abun-dant data with high throughput requires unhindered data movement through the interconnect network between the compute cores and the physical memory including methods for reconfiguring pathways on the fly. To address these fundamental challenges, we propose the synthesis, characterization, modelling, and benchmarking of radically different interconnect materials than are currently utilized by the industry. This includes new topological metals that do not require a barrier liner, classical metal alloys with engi-neered transport and scattering properties, and novel, ultra-thin barrier layers. Reconfigurable intercon-nects for dynamic tuning of the effective R-C will be realized through non-volatile (using low thermal budget ferroelectric gate stack) BEOL-compatible semiconducting oxide channel complementary transis-tors. Embedding of CMOS driver circuits in the back-end enables dynamic reconfiguration of the signal path while running a work load.
For microwave and mm-wave applications “interconnect” materials with higher electrical and thermal conductivity are also critical. Unfortunately, at high 10s of GHz frequencies, the skin effect, where eddy currents severely increase the resistance of RF conductors becomes an important bottleneck to higher performance transmission lines, antennas, inductors, and gates. Alleviating the skin effect is critical and our team has identified methods to mitigate the eddy currents providing up to 50% reduction in resistance above 30 GHz. Permeability tuning using superlattices of Cu and ferromagnetic materials enables an ele-gant path to resistance reduction up to 90 GHz relative to Cu alone, while strong spin-orbit interactions in topological metals suppress eddy currents and are expected to exhibit this advantage up to THz signals.
Current8 Research Tasks6 Universities22 Students8 Faculty Researchers48 Liaison Personnel
This Year43 Research Publications5 Patent Applications
Last Year8 Task Starts40 Research Publications1 Patent Applications
Since Inception8 Research Tasks6 Universities23 Students10 Faculty Researchers60 Liaison Personnel83 Research Publications6 Patent Applications