Request for White Papers in Advanced Devices Modeling & Simulation

The Semiconductor Industry has successfully scaled silicon-based information and signal-processing technologies to enable highly complex, affordable single-chip computer, communications and consumer electronic systems. This scaling has resulted in exponential improvements in cost and performance of microelectronics devices and circuits. Today, the Industry faces two highly daunting challenges. One is to sustain this silicon scaling over the next 10 - 15 years to its fundamental limit, and the second is to invent and develop a completely new universal information and signal-processing paradigm. The intent of this new paradigm is to extend microelectronics applications beyond the current ITRS time horizon to domains not accessible by conventional silicon CMOS technology. Modeling and simulation tools are anticipated to play important descriptive and guiding roles in research advancing CMOS to the end of the ITRS and in exploring new paradigms for information processing beyond CMOS.

In support of these objectives, SRC is soliciting white paper proposals for physically-based, predictive M&S tools, methodologies and benchmarking protocols that aid in obtaining improved understanding of innovative devices in the two areas listed below. Preference will be given to submissions that address ITRS nodes at and beyond the 45-nm node (18-nm physical gate length)

• Modeling and simulation of "known devices": These devices include but are not limited to non-classical CMOS devices [e.g., ultra-thin body MOS (e.g., fully depleted SOI), engineered channel device (i.e., strained Si/SiGe/SiGeC channels), double-gate MOS and 3D integrated structures (monolithic or hybrid integration) that leverage the silicon IC infrastructure. These devices and the proposed M&S tasks should address either or both digital and mixed signal applications. This will require significant extension of present prediction capabilities by including relevant physical mechanisms into canonical M&S tools and methodologies in order to assure broad applicability to this class of devices.
• Modeling and simulation of "novel devices": Examples of emerging nanoelectronic alternatives to CMOS devices (i.e., Novel Devices) may include (but are not limited to) coulomb-blockade-based devices, quantum dots, molecular electronics, carbon nanotubes, silicon nanowires, spin devices and 3D structures. These and other innovative devices based on novel materials and growth techniques may represent a paradigm shift in information processing, and will be more than a replacement for MOS transistors in the circuit; that is, such devices may require new circuit architectures. Thus, proposers can suggest tools and methodologies for the device M&S infrastructure as well as the M&S necessary to demonstrate the novel device/circuit interactions and structure.

Potential areas that are of interest (but not limited to) are:

• Improved understanding of nanoscale non-classical MOSFET structures (including the application of new materials to non-classical MOSFET structures)
• Atomistic and quantum scale modeling approaches that address device issues, interfaces and surfaces, gate stack (band structure, fixed charge, tunneling, trapping, etc.)
• Model carrier transport & dynamics (channel layer, high-K gate stack, source/drain, strained Si, SiGe, SiGeC, etc.)
• RF, analog and mixed signal modeling.
• Parametric fluctuations (doping, effective gate length, etc.)

White Paper Guidelines

The responses are to be three pages (or less) and be submitted by e-mail (PDF format) in order to facilitate our subsequent distribution to SRC Member Companies for review and evaluation.

Areas to be covered in the white paper are the following:

• Outline the current state of the art and describe the research that is planned. Discuss how it addresses the ITRS technology requirement for the 45-nm node (18-nm physical gate length) or beyond or addresses a novel approach not described on the ITRS roadmap. Please state the anticipated major research results.
• Address the facilities available to the researcher and give a brief CV of the investigator. Reference to a university web site is acceptable, but the proposed research will be evaluated based on the white paper itself.
• Anticipated Funding Request (plan for a 3-year program)
• Address your plan for an accelerated transfer of your technology to the software vendor community

Factors that would strengthen the proposal are:

• Addressing needs outlined in the document "2nd NSF/SRC/NIST Workshop: Nanotransistors: Technology, Physics, and Simulation"- a report of a workshop held at NIST on August 14 -15, 2001
• Linking the modeling and simulation tasks of this work with other faculty / institutions and/or National Labs exploring advanced technology ( experimental or simulation ) development.

This solicitation will close at 5:00 p.m. EDT on June 26, 2002. On August 2 an RFP will be requested for a 15-page proposal from those authors of white papers selected by the SRC Advanced Devices and Technologies TAB. These proposals are due to SRC by 5:00 p.m. EDT on August 30, 2002. The funding for proposals selected will commence on January 1, 2003. The contract award will be for a period of three years at a value commensurate with the objectives. Typical awards in the past have been based on one graduate student per task. We anticipate that 5-7 tasks will be awarded.

Please direct your responses to Shannon Geddes (geddes@src.org).