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Thrust/Theme
DCMOS – Digital CMOS Technologies
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- 1:
Method for Cleaning, Passivation and Functionalization of SI...
- Method for Cleaning, Passivation and Functionalization of SI-GE Semiconductor Sufraces Application Type: Divisional Patent Number: 10483097 Country: United States Status: Filed on ...
URL: https://www.src.org/library/patent/p1734/
Modified: 2019-11-19 - 25KB
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- 2:
Method for In-Situ Dry Cleaning, Passivation, Functionalization...
- Method for In-Situ Dry Cleaning, Passivation, Functionalization of SI-GE Semiconductor Surfaces Application Type: Utility Patent Number: 9818599 Country: United States Status: ...
URL: https://www.src.org/library/patent/p1429/
Modified: 2017-11-14 - 25KB
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- 3:
Method for in-SITU Dry Cleaning, Passivation, and Functionalization...
- Method for in-SITU Dry Cleaning, Passivation, and Functionalization of GE Semiconductor Surfaces Application Type: Utility Patent Number: 9117653 Country: United States Status: ...
URL: https://www.src.org/library/patent/p1477/
Modified: 2015-08-25 - 25KB
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- 4:
Methods of Fabricating Strained Semiconductor-On-Insulator Field...
- Methods of Fabricating Strained Semiconductor-On-Insulator Field-Effect Transistors And Related Devices Application Type: Utility Patent Number: 7211458 Country: United States ...
URL: https://www.src.org/library/patent/p0523/
Modified: 2007-05-01 - 22KB
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- 5:
Lanthanum Oxide-Based Gate Dielectrics for Integrated Circuit...
- Lanthanum Oxide-Based Gate Dielectrics for Integrated Circuit Field Effect Transistors and Methods of Fabricating Same Application Type: Foreign National Patent Number: NI154861 ...
URL: https://www.src.org/library/patent/p0580/
Modified: 2008-12-01 - 22KB
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- 6:
High Capacitance Density Gate Dielectrics for III-V Semiconductor...
- High Capacitance Density Gate Dielectrics for III-V Semiconductor Channels Using a Pre-Disposition Surface Treatment Involving Plasma and Ti Precursor Exposure Application Type: ...
URL: https://www.src.org/library/patent/p1506/
Modified: 2015-11-17 - 22KB
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