Managed Crosscuts
Overview
There are many semiconductor technology disciplines that are common to more than one science area. Research in one science area on a particular crosscut may be relevant to the needs in another science area for a particular crosscut. In order to maximize the benefits of crosscut research, GRC has implemented a management system for a number of important disciplines. The resulting management structure is matrix-like with managers assigned to coordinate crosscut research across science areas, and as needed, industry working groups are formed to overview research and identify research needs and gaps.
Research tasks are first classified by science area, then by a thrust within that science area, and may be assigned to one or more crosscuts.
3D
Manager: Jon Candelaria
The 3D crosscut tries to leverage process, design and packaging technologies for 3D IC stacking of strata to obtain better 3D system solutions. The focus of this research is on aggressive, high density approaches which deliver not only a smaller form factor, but higher inter-strata bandwidth, lower power and lower latency. While current application spaces include high bandwidth to memory solutions, 3D logic and system in a stack, the synergy across different science areas should drive more revolutionary applications and approaches. Current process technologies include thru silicon vias, inter-strata bonding, reliability and device parasitics. Design areas of interest include tools and techniques for 3D layout optimization, thermal mitigation strategies and optimal heterogeneous integration solutions. Packaging research focuses on thermal cooling solutions, high frequency performance and low cost / high yield stacking solutions. The above mentioned issues, as well as others, are addressed as crosscut items in the GRC portfolio.
Design for Manufacturability
Manager: Bill Joyner
The electronics industry is facing the prospect of not being able to fabricate products with acceptable performance, reliability, yield, and power consumption. The causes are increasing manufacturing and system variability, increasing design sensitivity, and decreasing design layout fidelity. Control of these factors is driving the need for significant improvement in materials, devices, interconnects, processes, design tools, and circuit and system architectures. Since these challenges span multiple science areas, inter-disciplinary collaboration will be key advances in this area. This cross thrust provides a global perspective of the design-manufacturing space to address the difficult challenges of variability at the ultimate limits of functional scaling, integration, and diversification. It also explores the necessary convergence of analog and digital design and fabrication requirements and corresponding performance-variability trade-offs. The ultimate goal is to enable two complementary opportunities: 1) How design information can be used to guide fabrication techniques; and 2) How new materials, processes, devices, interconnects, and packaging enable enhanced design capabilities.
Interconnect
Manager: Jon Candelaria
Interconnect includes the processes and designs associated with all of the IC structures necessary to connect from silicon on the IC to the boards and boxes of the outside world. Interconnect in this form has become a potential performance roadblock for the continuation of the semiconductor industry on the Moore's Law curve. This roadblock has technology components in areas such as speed limitations of on-chip metallization, high frequency limitations of packaging materials and structures, and power liabilities of the total interconnect system. This roadblock has design components related to the inability to do effective interconnect-centric design because of inadequate compact models, and inability to do accurate interconnect modeling in times compatible with design optimization use. Design roadblocks also exist in other areas, such as effective power distribution and lack of comprehensive power supply models for impact of crosstalk and ground bounce on analog and mixed signal devices. The above mentioned issues, as well as others, are addressed as crosscut items in the GRC portfolio.
Memory
Manager: Kwok Ng
The primary areas of interest for Memory crosscuts are: materials; processes; devices; circuits, components, and system designs. The main objectives of this crosscut are: materials development & characterization; linked with their associated circuit designs and architectures, addressing advanced memory technology needs at the 32nm node and beyond.
The strategy for the Memory crosscut is to establish inter-science area focus groups to refine memory research needs to launch an advisory group to prioritize common interscience area memory needs; and to develop leveraged research opportunities to support task force recommendations.
Metrology
Manager: Bob Havemann
The primary areas of interest for the Metrology crosscut are : materials; processes; devices; interconnects and packaging; circuit, component, and system design; and design automation. The main objectives of this crosscut are: characterization tools and methods, addressing strategic metrology gaps in advanced digital (less than or equal to 32nm) and analog/mixed signal (greater than or equal to 100nm) technologies.
The strategy for the Metrology crosscut is to establish inter-science area focus groups to refine metrology research needs; launch an advisory group to prioritize common interscience area metrology needs; and, to develop leveraged research opportunities to support task force recommendations.
Mixed Signal
Manager: David Yeh
Mixed Signal is a crosscut for research to enable ICs that integrate different signal domains, such as digital, analog, and RF, within a single chip or package. The main objective for the Mixed Signal crosscut is to develop techniques and technologies required to design and fabricate high performance, heterogeneous mixed-signal circuits in silicon, exploiting expertise across multiple science areas to enhance the capabilities of the overall system. Examples of this research are advanced design techniques for heterogeneous mixed signal systems; EDA tools which address the integration and optimization issues of combining analog, digital, and RF sub-systems into a single system; and advanced device and process architectures which provide excellent analog transistors and passive components within a leading-edge digital process.
The strategy for the Mixed Signal crosscut is to establish inter-science area focus groups to refine mixed signal research needs; launch an advisory group to prioritize common interscience area mixed signal needs; and to develop leveraged research opportunities to support task force recommendations.
Modeling & Simulation
Manager: Kwok Ng
Modeling & Simulation mathematically and computationally produces both numerical and visual descriptions of device performance and process results. This information is used to guide experimental directions towards the most promising alternatives to give detailed information to understand the results of experiments, and to provide views of performance for devices and processes that are beyond the range of current experimental investigation. Modeling & Simulation interfaces with fundamental science by incorporating the results of basic materials and device physics advances into process and device simulators. It also interfaces with circuit design through compact modeling programs to provide simulation capabilities appropriate for circuit design and device optimization. Modeling & Simulation for advanced CMOS devices, nanoscale devices, and the combination of nanoscale components with CMOS devices, needs to be multiscale and multi-phenomena. This area of modeling and simulation is highly interdisciplinary by nature, with developments occurring independently, but needing to be coordinated and coupled, across fields. The needs of Modeling & Simulation are addressed in a crosscut fashion throughout the science areas at GRC.
The strategy for the Modeling & Simulation crosscut is to establish inter-science area focus groups to refine modeling and simulation research needs; launch an advisory group to prioritize common interscience area modeling and simulation needs; and to develop leveraged research opportunities to support task force recommendations.
Multicore
Manager: William Joyner
In order to sustain the continued growth of computational performance, a paradigm shift in computing is needed to realize the full potential of highly and explicitly parallel - yet low power and resilient - computer systems. As scaling is made difficult by physical and power challenges, architectural innovations are the most likely means to achieve this increased performance. Parallel systems built from multicore processors that modularly integrate multiple, heterogeneous processor cores on a single chip promise computational performance enhancements for both high and low end computing platforms ranging from petaflops supercomputing systems to commodity computers and embedded systems. But there are many challenges to achieving this multicore success. Research is needed on hardware and software design; tools for design, test, and verification; architectures; and interconnect for multicore systems that will address all aspects of computing system design.
Reliability
Manager: Jon Candelaria
The projected advances of semiconductor technology in the next several years is anticipated to bring an unprecedented set of reliability challenges at levels that have not been seen in the history of the industry. The extensive number of new materials, new processes, novel devices, voltage scaling limitations, increasing power, die size, and package complexity will result in dramatic changes that threaten the virtually unlimited lifetime and high level of reliability that customers have come to expect, even as product complexity and performance has increased. In addition, increasing product complexity and performance are rapidly diminishing the effectiveness and even the ability to perform reliability testing at the product level. Perhaps the greatest concern in this area is that the directions of these changes are so diverse from current technology that most of these changes must occur without the benefit of the extended learning which has sustained this industry for the last 30 years. As a result, it is predictable that product cost and performance requirements will be substantially affected, and even superseded in many cases, by reliability constraints, unless new methods and new directions in reliability are established in all areas of design and process technology. These new directions are covered as a crosscut activity within the science area structure.
SRC-NSF Initiative for Silicon Nanoelectronics and Beyond (SNB)
Manager: Kwok Ng
In January of 2004, SRC and NSF signed a Memorandum of Understanding (MOU) to continue their long-standing partnership in the sponsorship of university research. An Addendum to the MOU defines a cooperative agreement for research in Silicon Nanoelectronics and Beyond as a theme area in the NSF Nanoscience and Engineering Initiative. Under the auspices of this agreement, SRC and NSF agree to work together to develop solicitations, to identify reviewers for submitted proposals, and to make available GRC technology transfer mechanisms including the participation of funded SNB researchers in GRC program reviews.
The SNB initiative is guided by a program committee responsible for the cooperative operation of the program and by a guidance committee designed to provide program oversight. Participation in the SRC technology transfer processes by NSF SNB awardees is on a voluntary basis. SNB projects are designated to be members of a crosscut in the GRC program structure since it is expected that projects funded will bridge the entire spectrum of semiconductor technology and design.
NSF-SRC Initiative for Nanotechnology
Manager: Bob Havemann
SRC and NSF have a Memorandum of Understanding (MOU) to continue their long-standing partnership in the sponsorship of university research. Under the auspices of this agreement, SRC and NSF agree to work together to develop solicitations, to identify reviewers for submitted proposals, and to make available GRC technology transfer mechanisms including the participation of funded NSF researchers in GRC program reviews. Participation in the SRC technology transfer processes by NSF awardees is on a voluntary basis. These projects are designated to be members of a crosscut in the GRC program structure since it is expected that projects funded will bridge the entire spectrum of semiconductor technology and design.
Software
Manager: David yeh
As overall system design has become more important, the emphasis on system optimization research has increased. This has increased the importance of software as a part of the overall system and thus, research that includes it is put into this crosscut. The optimization of embedded systems often includes operating system and application software as part of the overall power management, reliability, and quality-of-service strategy. In addition, multi-core systems performance may be limited by the underlying architecture and the software programming concurrency model. Thus, research into software as it relates to system optimization is included in this crosscut.