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Patent Filings
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- 1:
On-Chip IEC ESD Protection Using Parasitic PNP Devices (Patent...
- On-Chip IEC ESD Protection Using Parasitic PNP Devices Application Type: Utility Patent Number: 11094690 Country: United States Status: Filed on 24-Sep-2019, Issued on 17-Aug-2021 ...
URL: https://www.src.org/library/patent/p1849/
Modified: 2021-08-17 - 24KB
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- 2:
Sram Cell with Intrinsically High Stability and Low Leakage ...
- Sram Cell with Intrinsically High Stability and Low Leakage Application Type: Utility Patent Number: 7920409 Country: United States Status: Filed on 5-Jun-2007, Issued on ...
URL: https://www.src.org/library/patent/p1015/
Modified: 2011-04-05 - 24KB
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- 3:
DYNAMIC-ZOOM ANALOG TO DIGITAL CONVERTER (ADC) HAVING A COARSE...
- DYNAMIC-ZOOM ANALOG TO DIGITAL CONVERTER (ADC) HAVING A COARSE FLASH ADC AND A FINE PASSIVE SINGLE-BIT MODULATOR Application Type: Utility Patent Number: 10541706 Country: United ...
URL: https://www.src.org/library/patent/p1782/
Modified: 2020-01-21 - 26KB
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- 4:
Systems, Methods and Computer Program Products for Creating Hierarchic...
- Systems, Methods and Computer Program Products for Creating Hierarchical Equivalent Circuit Models Application Type: Utility Patent Number: 7096174 Country: United States Status: ...
URL: https://www.src.org/library/patent/p0200/
Modified: 2006-08-22 - 24KB
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- 5:
Graphene Device Including a PVA Layer or Formed Using a PVA Layer...
- Graphene Device Including a PVA Layer or Formed Using a PVA Layer Application Type: Continuation Patent Number: 8735209 Country: United States Status: Filed on 15-Mar-2013, Issued ...
URL: https://www.src.org/library/patent/p1404/
Modified: 2014-05-27 - 24KB
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- 6:
Method of Fabricating a Self-Aligned High Speed MOSFET Device...
- Method of Fabricating a Self-Aligned High Speed MOSFET Device Application Type: Continuation (in part) Patent Number: 5599728 Country: United States Status: Filed on 28-Oct-1994, ...
URL: https://www.src.org/library/patent/p0006/
Modified: 1997-02-04 - 22KB
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- 7:
Wire Width Planning and Performance Optimization for VLSI Interconnect...
- Wire Width Planning and Performance Optimization for VLSI Interconnects Application Type: Utility Patent Number: 6408427 Country: United States Status: Filed on 22-Feb-2000, Issued ...
URL: https://www.src.org/library/patent/p0001/
Modified: 2002-06-18 - 29KB
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- 8:
High-Performance Gate Oxides such as for Graphene Field-Effect...
- High-Performance Gate Oxides such as for Graphene Field-Effect Transistors or Carbon Nanotubes Application Type: Utility Patent Number: 8445893 Country: United States Status: Filed ...
URL: https://www.src.org/library/patent/p1209/
Modified: 2013-05-21 - 24KB
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