[x]
Content Type
Patent Filings
[x]
Thrust/Theme
TT – Test & Testability
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| 1 through 16 of
16 similar documents, best matches first. |
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- 1:
Power Switch Design and Method for Reducing Leakage Power in...
- Power Switch Design and Method for Reducing Leakage Power in Low-Power Integrated Circuits Application Type: Utility Patent Number: 8373493 Country: United States Status: Filed on ...
URL: https://www.src.org/library/patent/p1239/
Modified: 2013-02-12 - 22KB
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- 2:
Testing Monolithic Three Dimensional Integrated Circuits (Patent...
- Testing Monolithic Three Dimensional Integrated Circuits Application Type: Utility Patent Number: 10775429 Country: United States Status: Filed on 2-Nov-2017, Issued on 15-Sep-2020 ...
URL: https://www.src.org/library/patent/p1746/
Modified: 2020-09-15 - 25KB
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- 3:
Methods for Characterizing, Generating Test Sequences for, and...
- Methods for Characterizing, Generating Test Sequences for, and Simulating Integrated Circuit Faults Using Fault Tuples and Related Systems and Computer Program Products Application ...
URL: https://www.src.org/library/patent/p0228/
Modified: 2004-12-28 - 22KB
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- 4:
Multi-Layer Integrated Circuits Having Isolation Cells for Layer...
- Multi-Layer Integrated Circuits Having Isolation Cells for Layer Testing and Related Methods Application Type: Continuation (in part) Patent Number: 10838003 Country: United States ...
URL: https://www.src.org/library/patent/p1826/
Modified: 2020-11-17 - 25KB
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- 5:
Multi-Layer Integrated Circuits Having Isolation Cells for Layer...
- Multi-Layer Integrated Circuits Having Isolation Cells for Layer Testing and Related Methods Application Type: Utility Patent Number: 10338133 Country: United States Status: Filed ...
URL: https://www.src.org/library/patent/p1639/
Modified: 2019-07-02 - 25KB
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- 6:
Software-Based Self-Test and Diagnosis Using On-Chip Memory ...
- Software-Based Self-Test and Diagnosis Using On-Chip Memory Application Type: Utility Patent Number: 9864007 Country: United States Status: Filed on 30-Apr-2014, Issued on ...
URL: https://www.src.org/library/patent/p1457/
Modified: 2018-01-09 - 25KB
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- 7:
Signal Tracing Using On-Chip Memory For In-System Post-Fabrication...
- Signal Tracing Using On-Chip Memory For In-System Post-Fabrication Debug Application Type: Utility Patent Number: 9720036 Country: United States Status: Filed on 18-Aug-2014, ...
URL: https://www.src.org/library/patent/p1495/
Modified: 2017-08-01 - 23KB
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- 8:
Signal Tracing using ON-Chip Memory for In-System Post-Fabrication...
- Signal Tracing using ON-Chip Memory for In-System Post-Fabrication Debug Application Type: Continuation Patent Number: 10732221 Country: United States Status: Filed on 26-Jun-2017, ...
URL: https://www.src.org/library/patent/p1733/
Modified: 2020-08-04 - 24KB
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- 9:
Software-Based Self-Test and Diagnosis Using on-Chip Memory ...
- Software-Based Self-Test and Diagnosis Using on-Chip Memory Application Type: Divisional Patent Number: 10788532 Country: United States Status: Filed on 30-Nov-2017, Issued on ...
URL: https://www.src.org/library/patent/p1753/
Modified: 2020-09-29 - 26KB
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- 10:
Software-Based Self-Test and Diagnosis Using on-Chip Memory ...
- Software-Based Self-Test and Diagnosis Using on-Chip Memory Application Type: Divisional Patent Number: 10845416 Country: United States Status: Filed on 30-Nov-2017, Issued on ...
URL: https://www.src.org/library/patent/p1752/
Modified: 2020-11-24 - 26KB
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- 11:
Method and Architecture for Pre-bond Probing of TSVs in 3D Stacked...
- Method and Architecture for Pre-bond Probing of TSVs in 3D Stacked Integrated Circuits Application Type: Utility Patent Number: 8775108 Country: United States Status: Filed on ...
URL: https://www.src.org/library/patent/p1291/
Modified: 2014-07-08 - 22KB
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- 12:
Scan Test of Die Logic in 3D ICs Using TSV Probing (Patent P1368...
- Scan Test of Die Logic in 3D ICs Using TSV Probing Application Type: Utility Patent Number: 8782479 Country: United States Status: Filed on 1-Nov-2012, Issued on 15-Jul-2014, ...
URL: https://www.src.org/library/patent/p1368/
Modified: 2014-07-15 - 22KB
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- 13:
Retiming-Based Design Flow for Delay Recovery on Inter-Die Paths...
- Retiming-Based Design Flow for Delay Recovery on Inter-Die Paths in 3D ICs Application Type: Utility Patent Number: 8832608 Country: United States Status: Filed on 17-Jun-2013, ...
URL: https://www.src.org/library/patent/p1411/
Modified: 2014-09-09 - 22KB
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- 14:
Method for Automatically Generating Test Vectors for Digital...
- Method for Automatically Generating Test Vectors for Digital Integrated Circuits Application Type: Utility Patent Number: 5377197 Country: United States Status: Filed on ...
URL: https://www.src.org/library/patent/p0059/
Modified: 1994-12-27 - 22KB
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- 15:
Non-Invasive Pre-Bond TSV TestUsing Ring Oscillators and Multiple...
- Non-Invasive Pre-Bond TSV TestUsing Ring Oscillators and Multiple Voltage Levels Application Type: Utility Patent Number: 9478720 Country: United States Status: Filed on ...
URL: https://www.src.org/library/patent/p1392/
Modified: 2016-11-01 - 24KB
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- 16:
Non-Invasive Pre-Bond TSV Test using Ring Oscillators and Multiple...
- Non-Invasive Pre-Bond TSV Test using Ring Oscillators and Multiple Voltage Levels Application Type: Continuation Patent Number: 10444279 Country: United States Status: Filed on ...
URL: https://www.src.org/library/patent/p1635/
Modified: 2019-10-15 - 23KB
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