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SRC Program
GRC 196
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STARnet 20
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NRI 7
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C2S2 23
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GSRC 12
ACE4S 9
C-FAR 8
C-SPIN 8
IFC 8
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CRISP 5
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CNFD 2
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CD – Circuit Design 38
TT – Test & Testability 30
LPD – Logic & Physical Design 17
ASCENT-T1 – Vertical CMOS 12
AMS-CSD – Analog/Mixed-Signal Ci... 11
CADT – Computer-Aided Design and... 10
HWS – Hardware Security 10
I3T – Innovative and Intelligent... 10
ISD – Integrated System Design 10
SLD – System Level Design 10
Advanced Devices & Technologies 9
ASCENT-T2 – Beyond CMOS 8
NMP – Nanomanufacturing Material... 7
ADS – Alternative Device Structu... 6
DesTech – Design Techniques 6
Factory Systems 6
AMML-T1 – Antiferromagnetic Magn... 5
CRISP-T1 – Hardware Support for ... 4
Physical Design 4
BEP – Back End Processes 3
PKG – Packaging 3
TechCAD – Technology CAD 3
Back End Processes 2
DCMOS – Digital CMOS Technologie... 2
DesSyn – Design Synthesis 2
IMPACT-T1 – Materials for Scaled... 2
Masks 2
Materials 2
PAT – Patterning 2
VER – Verification 2
ASCENT-T4 – Merged Logic Memory ... 1
CAPSL-T4 – Architectures and Sys... 1
CM – Compact Modeling 1
CRISP-T3 – Scaling Applications ... 1
ComSenTer-T1 – Systems and Algor... 1
DEEP3M-T2 – Circuits 1
DEEP3M-T4 – Architectures 1
DV – Design Verification 1
IMPACT-T2 – Materials for Storag... 1
Modeling & Simulation 1
NEWLIMITS-T1 – Novel Computing a... 1
NEWLIMITS-T4 – Characterization ... 1
Reliability 1
SemiSynBio – Semiconductor Synth... 1
Synthesis & Verification 1
GRC Science Area
CADTS – Computer Aided Design & ... 67
ICSS – Integrated Circuit & Syst... 57
DES – Design Sciences 25
NIS – Nanostructure & Integratio... 20
MPS – Material & Process Science... 14
IPS – Interconnect & Packaging S... 9
MIC – Microstructure Sciences 9
PID – Process Integration & Devi... 9
MBP – Materials & Bulk Processes... 8
DS – Device Sciences 5
NMS – Nanomanufacturing Sciences 5
LIT – Lithography Sciences 3
INT – Interconnect Sciences 2
MFGPS – Manufacturing Process Sc... 1
1 through 30 of 302 similar documents, best matches first.   
Results by:Thunderstone Page: 1 2 3 4 5 6 7 8 9 10 next >>
1: Method and System for Synthesizing Relative Timing Constraints...
Method and System for Synthesizing Relative Timing Constraints on an Integrated Circuit Design to Facilitate Timing Verification Application Type: Continuation Patent Number: ...
URL: https://www.src.org/library/patent/p1354/
Modified: 2012-11-27 - 24KB
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2: Method and System for Synthesizing Relative Timing Constraints...
Method and System for Synthesizing Relative Timing Constraints on an Integrated Circuit Design to Facilitate Timing Verification Application Type: Utility Patent Number: 8239796 ...
URL: https://www.src.org/library/patent/p1202/
Modified: 2012-08-07 - 24KB
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3: Methods, Apparatus and Computer Program products for Synthesizing...
Methods, Apparatus and Computer Program products for Synthesizing Integrated Circuits with Electrostatic Discharge Capability and Correcting Ground Rule Faults Therein Application ...
URL: https://www.src.org/library/patent/p0049/
Modified: 1998-08-18 - 27KB
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4: Tunable Integrated Circuit Design for Nano-Scale Technologies...
Tunable Integrated Circuit Design for Nano-Scale Technologies Application Type: Utility Patent Number: 7945868 Country: United States Status: Filed on 1-Oct-2008, Issued on ...
URL: https://www.src.org/library/patent/p1106/
Modified: 2011-05-17 - 22KB
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5: Testing Monolithic Three Dimensional Integrated Circuits (Patent...
Testing Monolithic Three Dimensional Integrated Circuits Application Type: Utility Patent Number: 10775429 Country: United States Status: Filed on 2-Nov-2017, Issued on 15-Sep-2020 ...
URL: https://www.src.org/library/patent/p1746/
Modified: 2020-09-15 - 25KB
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6: Method and System for Performing Global Routing on an Integrated...
Method and System for Performing Global Routing on an Integrated Circuit Design Application Type: Utility Patent Number: 7661085 Country: United States Status: Filed on ...
URL: https://www.src.org/library/patent/p1032/
Modified: 2010-02-09 - 22KB
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7: Self-Timing Integrated Circuits Having Low Clock Signal during...
Self-Timing Integrated Circuits Having Low Clock Signal during Inactive Periods Application Type: Utility Patent Number: 5324992 Country: United States Status: Filed on 1-Jul-1992, ...
URL: https://www.src.org/library/patent/p0232/
Modified: 1994-06-28 - 21KB
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8: ESD/EOS Protection Circuits for Integrated Circuits (Patent P0074...
ESD/EOS Protection Circuits for Integrated Circuits Application Type: Utility Patent Number: 5450267 Country: United States Status: Filed on 31-Mar-1993, Issued on 12-Sep-1995, ...
URL: https://www.src.org/library/patent/p0074/
Modified: 1995-09-12 - 25KB
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9: Floorplan Evaluation, Global Routing, and Buffer Insertion for...
Floorplan Evaluation, Global Routing, and Buffer Insertion for Integrated Circuits Application Type: Utility Patent Number: 7062743 Country: United States Status: Filed on ...
URL: https://www.src.org/library/patent/p0405/
Modified: 2006-06-13 - 21KB
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10: Built-in Current Testing of Integrated Circuits (Patent P0109...
Built-in Current Testing of Integrated Circuits Application Type: Utility Patent Number: 5025344 Country: United States Status: Filed on 22-Feb-1990, Issued on 18-Jun-1991, Patent ...
URL: https://www.src.org/library/patent/p0109/
Modified: 1991-06-18 - 22KB
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11: Method and Architecture for Pre-bond Probing of TSVs in 3D Stacked...
Method and Architecture for Pre-bond Probing of TSVs in 3D Stacked Integrated Circuits Application Type: Utility Patent Number: 8775108 Country: United States Status: Filed on ...
URL: https://www.src.org/library/patent/p1291/
Modified: 2014-07-08 - 22KB
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12: Multi-Layer Integrated Circuits Having Isolation Cells for Layer...
Multi-Layer Integrated Circuits Having Isolation Cells for Layer Testing and Related Methods Application Type: Continuation (in part) Patent Number: 10838003 Country: United States ...
URL: https://www.src.org/library/patent/p1826/
Modified: 2020-11-17 - 25KB
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13: Multi-Layer Integrated Circuits Having Isolation Cells for Layer...
Multi-Layer Integrated Circuits Having Isolation Cells for Layer Testing and Related Methods Application Type: Utility Patent Number: 10338133 Country: United States Status: Filed ...
URL: https://www.src.org/library/patent/p1639/
Modified: 2019-07-02 - 25KB
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14: Power Switch Design and Method for Reducing Leakage Power in...
Power Switch Design and Method for Reducing Leakage Power in Low-Power Integrated Circuits Application Type: Utility Patent Number: 8373493 Country: United States Status: Filed on ...
URL: https://www.src.org/library/patent/p1239/
Modified: 2013-02-12 - 22KB
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15: Method for Automatically Generating Test Vectors for Digital...
Method for Automatically Generating Test Vectors for Digital Integrated Circuits Application Type: Utility Patent Number: 5377197 Country: United States Status: Filed on ...
URL: https://www.src.org/library/patent/p0059/
Modified: 1994-12-27 - 22KB
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16: Source Contact Placement for Efficient ESD/EOS Protection in...
Source Contact Placement for Efficient ESD/EOS Protection in Grounded Substrate MOS Integrated Circuit Application Type: Utility Patent Number: 5404041 Country: United States ...
URL: https://www.src.org/library/patent/p0067/
Modified: 1995-04-04 - 25KB
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17: Method of Forming Boron Carbo-Nitride Layers for Integrated Circuit...
Method of Forming Boron Carbo-Nitride Layers for Integrated Circuit Devices Application Type: Utility Patent Number: 7144803 Country: United States Status: Filed on 16-Apr-2004, ...
URL: https://www.src.org/library/patent/p0451/
Modified: 2006-12-05 - 22KB
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18: Method of placing source contacts for efficient EDS\EOS protection...
Method of placing source contacts for efficient EDS\EOS protection in grounded substrate MOS integrated circuit Application Type: Divisional Patent Number: 5468667 Country: United ...
URL: https://www.src.org/library/patent/p0373/
Modified: 1995-11-21 - 22KB
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19: System and Method to Test Integrated Circuits on a Wafer (Patent...
System and Method to Test Integrated Circuits on a Wafer Application Type: Utility Patent Number: 7325180 Country: United States Status: Filed on 26-Nov-2003, Issued on ...
URL: https://www.src.org/library/patent/p0413/
Modified: 2008-01-29 - 22KB
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20: Method and System for Modeling Uncertainties in Integrated Circuits...
Method and System for Modeling Uncertainties in Integrated Circuits, Systems, and Fabrication Processes Application Type: Utility Patent Number: 7920992 Country: United States ...
URL: https://www.src.org/library/patent/p0625/
Modified: 2011-04-05 - 22KB
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21: Method and Apparatus for Designing Circuits Using High-Level...
Method and Apparatus for Designing Circuits Using High-Level Synthesis Application Type: Utility Patent Number: 7383529 Country: United States Status: Filed on 14-Feb-2005, Issued ...
URL: https://www.src.org/library/patent/p0529/
Modified: 2008-06-03 - 23KB
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22: Method and Circuit for Reducing Leakage and Increasing Read Stability...
Method and Circuit for Reducing Leakage and Increasing Read Stability in a Memory Device Application Type: Utility Patent Number: 7328413 Country: United States Status: Filed on ...
URL: https://www.src.org/library/patent/p0486/
Modified: 2008-02-05 - 22KB
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23: Methods of Generating Integrated Circuit (IC) Layout Synthetic...
Methods of Generating Integrated Circuit (IC) Layout Synthetic Patterns and Related Computer Program Products Application Type: Utility Patent Number: 11449658 Country: United ...
URL: https://www.src.org/library/patent/p1862/
Modified: 2022-09-20 - 24KB
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24: Retiming-Based Design Flow for Delay Recovery on Inter-Die Paths...
Retiming-Based Design Flow for Delay Recovery on Inter-Die Paths in 3D ICs Application Type: Utility Patent Number: 8832608 Country: United States Status: Filed on 17-Jun-2013, ...
URL: https://www.src.org/library/patent/p1411/
Modified: 2014-09-09 - 22KB
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25: Dynamic Functional Obfuscation (Patent P1727) - SRC
Dynamic Functional Obfuscation Application Type: Utility Patent Number: 11061997 Country: United States Status: Filed on 3-Aug-2017, Issued on 13-Jul-2021 Organization: University ...
URL: https://www.src.org/library/patent/p1727/
Modified: 2021-07-13 - 27KB
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26: Software-Based Self-Test and Diagnosis Using on-Chip Memory ...
Software-Based Self-Test and Diagnosis Using on-Chip Memory Application Type: Divisional Patent Number: 10788532 Country: United States Status: Filed on 30-Nov-2017, Issued on ...
URL: https://www.src.org/library/patent/p1753/
Modified: 2020-09-29 - 26KB
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27: Software-Based Self-Test and Diagnosis Using on-Chip Memory ...
Software-Based Self-Test and Diagnosis Using on-Chip Memory Application Type: Divisional Patent Number: 10845416 Country: United States Status: Filed on 30-Nov-2017, Issued on ...
URL: https://www.src.org/library/patent/p1752/
Modified: 2020-11-24 - 26KB
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28: Software-Based Self-Test and Diagnosis Using On-Chip Memory ...
Software-Based Self-Test and Diagnosis Using On-Chip Memory Application Type: Utility Patent Number: 9864007 Country: United States Status: Filed on 30-Apr-2014, Issued on ...
URL: https://www.src.org/library/patent/p1457/
Modified: 2018-01-09 - 25KB
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29: Signal Tracing Using On-Chip Memory For In-System Post-Fabrication...
Signal Tracing Using On-Chip Memory For In-System Post-Fabrication Debug Application Type: Utility Patent Number: 9720036 Country: United States Status: Filed on 18-Aug-2014, ...
URL: https://www.src.org/library/patent/p1495/
Modified: 2017-08-01 - 23KB
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30: Signal Tracing using ON-Chip Memory for In-System Post-Fabrication...
Signal Tracing using ON-Chip Memory for In-System Post-Fabrication Debug Application Type: Continuation Patent Number: 10732221 Country: United States Status: Filed on 26-Jun-2017, ...
URL: https://www.src.org/library/patent/p1733/
Modified: 2020-08-04 - 24KB
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1 through 30 of 302 similar documents, best matches first.   
Results by:Thunderstone Page: 1 2 3 4 5 6 7 8 9 10 next >>