Method and System for Synthesizing Relative Timing Constraints on an Integrated Circuit Design to Facilitate Timing Verification

    • Application Type:
      Utility
      Patent Number:
      8239796
      Country:
      United States
      Status:
      Filed on 2-Mar-2010, Issued on 7-Aug-2012
      Organization:
      University of Utah
      SRC Filing ID:
      P1202

    Inventors

    • Yang Xu (Univ. of Utah)
    • Kenneth Stevens (Univ. of Utah)

    Related Patents

    P1184
    Application Expired
    GRC

    Method and System for Synthesizing Relative Timing Constraints on an Integrated Circuit Design Before Performing Timing Verification

    Kenneth Stevens (Univ. of Utah); Yang Xu (Univ. of Utah)
    Patent Application Expired
    Application Type: Provisional
    P1354
    Abandoned Patent
    GRC

    Method and System for Synthesizing Relative Timing Constraints on an Integrated Circuit Design to Facilitate Timing Verification

    Kenneth Stevens (Univ. of Utah); Yang Xu (Univ. of Utah)
    Patent Abandoned
    Application Type: Continuation

    INFORMATION

    FOR MEMBERS

    SRC VALUE

    ACADEMIA

    4819 Emperor Blvd, Suite 300 Durham, NC 27703 Voice: (919) 941-9400 Fax: (919) 941-9450

    © 2024 by Semiconductor Research Corporation ®
    Access to information on this website may be limited to member companies,
    participating agencies, and qualified researchers.

    Important Information for the SRC website. This site uses cookies to store information on your computer. By continuing to use our site, you consent to our cookies. If you are not happy with the use of these cookies, please review our Cookie Policy to learn how they can be disabled. By disabling cookies, some features of the site will not work.