Floorplan Evaluation, Global Routing, and Buffer Insertion for Integrated Circuits

    • Application Type:
      Utility
      Patent Number:
      7062743
      Country:
      United States
      Status:
      Filed on 24-Sep-2003, Issued on 13-Jun-2006, Patent Abandoned
      Organization:
      University of California, San Diego
      SRC Filing ID:
      P0405

    Inventor

    • Andrew Kahng (UC/San Diego)

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    Application Type: Provisional

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