Abstract: Future Energy Efficient Many-Core Processing
Bevan Baas
Department of Computer & Electrical Engineering
Univ. of California/Davis
Future fabrication technologies are expected to provide ever-increasing numbers of available devices but both system-level and chip-level power constraints will limit achievable throughputs--thus highlighting the criticalness of energy-efficient design. Die device counts in the 100s of millions and billions virtually guarantee designs will have many processors and the most interesting research questions deal with how the available devices and wires are organized into 100s and 1000s of processing elements per die.
The most high performance, energy efficient, and smallest area designs will have processing units matched to their computational kernels in terms of datapath complexity, data memory requirements, and instruction stream requirements. Further optimized designs will match their supply voltage and clock frequency to the processor's instantaneous workload demands.
To fully realize the benefits of many-core processor arrays, research breakthroughs will be required in the following areas among others:
- Study of processing element granularities on the entire spectrum from FPGA logic blocks to complex processors, driven by application requirements
- Support for, optimization of, and control of (joint global and local) independent supply voltage and clock frequency domains
- Study of the benefits and limitations of design points along the general-purpose to specialized-processor continuum
- Efficient, scalable, VLSI-driven networks on chip
- Tools for programming, task placement, modeling, and debugging of chips with 1000s of processors
