Research Opportunities to Address Patterning Challenges in the sub-10 nm Era

Moshe Preil
Manager of Emerging Lithography and Tools
GLOBALFOUNDRIES

As the semiconductor industry celebrates the 50th anniversary of Moore’s Law, most of the attention has been paid to the steady decline in feature sizes achieved over the past half century through the three basic parameters which define resolution according to the Rayleigh equation: wavelength, numerical aperture (NA) and k1 factor. Over the past decade, however, there has been almost no improvement in any of these three parameters. The wavelength has not changed since the adoption of 193 nm ArF excimer light sources, the maximum of NA of 1.35 (0.93 * the index of refraction of water) has been reached, and the k1 factor is already at the lowest practical value of ~ 0.30. Despite this, progress in increasing patterning density has continued through novel processes such as multiple patterning through sidewall deposition of litho-etch-litho-etch double patterning. In many respects, the limiting feature sizes are now being defined by deposition and etch processes rather than by the optical patterning step.

This trend has created new pressures in other parts of the patterning process, beginning with the design itself. It is no longer feasible to print random, 2D patterns. The most critical layers are restricted to unidirectional patterns with a limited range of critical dimensions (CD) and pitch. Multiple patterning has put greater stress on total overlay (OL) budgets – even a single nm of additional overlay error can be critical. The traditional breakdown of lithographic error budgets into CD and OL tolerances has given way to total edge placement error (EPE) budgets where both CD and OL, as well as film and etch variations, must be controlled together to meet the required tolerances. Contact hole and cut mask placement have likewise been tightened to single digit EPE budgets.

SRC funded research has contributed – and will continue to play a key role – to potential solutions such as directed self-assembly (DSA), selective deposition and etch,, and design methodologies for restricted design rules and multiple patterning. In the future, research must focus not just on individual parts of the process and design but on design and process co-optimization (DTCO) to produce manufacturable parts. Selective deposition and etch may well improve overlay tolerances by growing or removing materials only in specific areas, but this must be accomplished without leaving residues on the wrong parts of the wafer. Similarly, while DSA reduces the CD variation of traditional top-down processing, the placement of the self-assembled patterns can degrade overlay performance. DSA is also suited only for very restricted sets of patterns, requiring tighter coupling between design and process.

There are also significant materials challenges to be addressed. New “gate all around” (GAA) architectures will require vertical selectivity as well as horizontal patterning. While the exact GAA configuration is not yet settled, both nanowire and nanosheet options may be needed, and new methods of connecting laterally rather than vertically will present new process and metrology challenges. Finally, improvements in resist and other materials must take into account the stochastic nature of patterning processes at such small dimensions. Improved materials and simulation tools are needed to develop processes which produce uniform, predictable results in a domain where molecular level variations take place over a significant fraction of the feature size.