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SRC/SIA Webinar: Advances and Challenges in Semiconductor Hardware

Date:

Thursday, June 23, 2022, 12:30 p.m.–2 p.m. ET

Location:

Webinar, Washington, DC, United States

Event ID:

E007664

Purpose

The SRC-DARPA JUMP program reignited semiconductor hardware innovation in many areas. Examples include transcending the current limitations of 2D planar integrated circuits by pioneering 3D monolithic and heterogeneously integration, new and application-driven architecture and system-driven technologies, communication technologies, autonomous intelligence based on brain-inspired information processing, etc. Research topics include, but are not limited to, cognitive computing, technologies for a future cellular infrastructure, foundational material synthesis routes and device technologies to support the next era of “functional hyper-scaling.”

The main goal of the webinar is to present the “success stories” from SRC’s JUMP program and identify a compelling research agenda for the next wave of Semiconductor manufacturing based on the Decadal Plan for Semiconductors.

Participants

Welcome Remarks

Eric Breckenfeld is the Director of Technology Policy at the Semiconductor Industry Association (SIA), where he directs SIA’s research and development activities as well as the association’s education and workforce development efforts. Prior to joining SIA, Eric was a Lead Scientist at Booz Allen Hamilton where he served as a consultant for predominantly U.S. defense clients, including DARPA and the U.S. Naval Sea Systems Command in the areas of electronic materials and device physics, robotics and autonomy, and hardware/supply chain security. Before joining Booz Allen Hamilton, Eric was an AAAS Science and Technology Policy Fellow with the White House’s National Nanotechnology Initiative where he led the Sustainable Nanomanufacturing and Nanoelectronics for 2020 and Beyond initiatives. Previously, Eric was a National Research Council Fellow at the Naval Research Laboratory. Eric received his B.S. degree in Physics from the University of Wisconsin-Madison and his Ph.D. in Materials Science and Engineering from the University of Illinois Urbana-Champaign. He remains very passionate about STEM education outreach and improving the public’s STEM literacy. Toward this, he helped found a board game design competition with the Champaign Urbana Design Organization (CUDO) called “CUDO Plays” which teaches the public to use makerspace tools, and which is still running today.

Opening Remarks

Dev Palmer is the JUMP Program Manager and the Deputy Director of the DARPA Microsystems Technology Office, where he works closely with the Office Director to set strategy, guide the development of new programs and the execution of existing programs, and identify and recruit new Program Managers. Prior to joining DARPA, he was Chief Technologist at Lockheed Martin Advanced Technology Laboratories where he directed the independent research and development program and implemented technology strategy. Earlier in his career, he directed a portfolio of programs ranging from basic research to advanced technology transition in Program Manager roles at DARPA and the Army Research Office. Dr. Palmer is a Fellow of the IEEE, author on over 100 publications and presentations, and inventor on four US patents.

Presenter

Suman Datta Suman Datta is the Stinson Professor of Nanotechnology in the Electrical Engineering Department at the University of Notre Dame. In Fall, he will be joining the faculty of the School of Electrical & Computer Engineering at Georgia Tech as Joseph M Pettit Chair in Advanced Computing and Georgia Research Alliance (GRA) Eminent Scholar. Prior to that, he was a Professor of Electrical Engineering at The Pennsylvania State University, University Park, from 2007 to 2011. From 1999 till 2007, he was in the Advanced Transistor Group at Intel Corporation, Hillsboro, where he led device R&D effort for several generations of high-performance logic transistor technologies such as high-k/metal gate, Tri-gate and non-silicon channel CMOS transistor technologies. His research group focuses on emerging device concepts that enable new computational models such as in-memory compute, cognitive compute, cryogenic compute etc. He is a Fellow of the IEEE and the National Academy of Inventors (NAI). He has published over 400 journal and refereed conference papers and holds 187 patents related to semiconductor devices. He is the Director of a multi-university advanced microelectronics research center, the ASCENT, funded by the Semiconductor Research Corporation (SRC) and the Defense Advanced Research Projects Agency (DARPA).

Panelists

	Madhavan Swaminathan is the John Pippin Chair in Microsystems Packaging & Electromagnetics in the School of Electrical and Computer Engineering (ECE), Professor in ECE with a joint appointment in the School of Materials Science and Engineering (MSE), and Director of the 3D Systems Packaging Research Center (PRC), Georgia Tech (GT). He also serves as the Site Director for the NSF Center for Advanced Electronics through Machine Learning and Theme Leader for Heterogeneous Integration, at the SRC JUMP ASCENT Center. Prior to joining GT, he was with IBM working on packaging for supercomputers. He is the author of 550+ refereed technical publications and holds 31 patents. He is the primary author and co-editor of 3 books and 5 book chapters, founder and co-founder of two start-up companies, and founder of the IEEE Conference on Electrical Design of Advanced Packaging and Systems (EDAPS), a premier conference sponsored by the IEEE Electronics Packaging Society (EPS) currently in its 20th year. He is an IEEE Fellow and has served as the Distinguished Lecturer for the IEEE Electromagnetic Compatibility (EMC) society. He received his MS and PhD degrees in Electrical Engineering from Syracuse University in 1989 and 1991, respectively.
	Srabanti Chowdhury of Electrical Engineering, leads the wideband gap lab (WBG-Lab) at Stanford where her group focuses on materials and device research for high frequency and energy-efficient solutions for compact systems as well as their thermal management. She serves as the Science Collaboration Director of the Energy Frontier Research Center (EFRC), ULTRA, supported by the US Department of Energy. She received her M.S and Ph.D. in Electrical Engineering from UCSB. She has received multiple early career awards, including the Young Scientist award by the International Symposium on Compound Semiconductors and the Alfred P. Sloan research fellowship in Physics. She serves in several technical program committee including IEEE VLSI and IRPS, and the executive committee of IEDM. To date, her research has produced over 100 journal papers, 150 conference presentations and 26 issued patents.
	Vijaykrishnan Narayananis the Robert Noll Chair of Computer Science and Engineering at The Pennsylvania State University. His research interests are in computer architecture, design using emerging technologies, and embedded systems. He is a recipient of the 2021 IEEE Computer Society Edward McCluskey Technical Achievement Award, and 2021 IEEECS TCVLSI Distinguished Research Award. He serves as the Associate Director of the DoE 3DFeM Center, a thrust leader for the DARPA/SRC Center for Brain Inspired Computing and a PI for SRC CRISP. He is a Fellow of the IEEE, ACM and National Academy of Inventors.
	X. Sharon Hu is a professor in the department of Computer Science and Engineering at the University of Notre Dame, USA. Her research interests include low-power system design, circuit and architecture design with emerging technologies, real-time embedded systems and hardware-software co-design. She has published more than 400 papers in these areas. Some of her recognitions include the Best Paper Award from the Design Automation Conference and the International Symposium on Low Power Electronics and Design, and NSF Career award. She has participated in several large industry and government sponsored center-level projects and was a theme lead in an NSF/SRC E2CDA project. She served as the General Chair and TPC Chair of Design Automation Conference, Real-Time Systems Symposium, etc. She is the Editor-in-Chief of ACM Transactions on Design Automation of Electronic Systems, and has also served as Associate Editor for a number of ACM and IEEE journals. X. Sharon Hu is a Fellow of the ACM and a Fellow of the IEEE.
	Farhana Sheikhis a Principal Engineer at Intel’s Programmable Solution Group’s CTO & Strategy Office. She has over 15 years of experience in ASIC and DSP/communications research including adaptive DSP, crypto, graphics, quantum wireless control, and 5G+ wireless. Since joining PSG, after 10+ years in Intel Labs, Farhana’s research focuses on 2-D and 3-D chiplet + FPGA integration research, with a focus on 3D heterogeneous integration for next generation wireless and sensing applications. Farhana has published over 50 papers and filed 22 patents, has initiated the AIB-3D open-source specification for 3D chiplet heterogeneous integration. Farhana was instrumental in enabling Intel 16 for Intel’s IDM2.0 and is the co-creator of Intel’s University Shuttle Program. Outside of Intel she volunteers for IEEE Solid-State Circuits Society (SSCS) and is the SSCS Women in Circuits Committee Chair. Farhana is a co-recipient of 2020, 2019, and 2012 IEEE ISSCC Outstanding Paper Awards. In 2021, Farhana was recognized for her mentorship work with students and faculty by the Semiconductor Research Corporation (SRC) that awarded her the 2021 Mahboob Khan Outstanding Industry Liaison Award. Recently, she was elected IEEE SSCS Member-at-Large for 2022-2024.

Roundtable Moderator

Zoran Zvonar is the Fellow and Director, University Programs, CTO Office Analog Devices, Inc (ADI). In his current role he is responsible for ADI’s external research engagements worldwide. Previously, 1994-2008, he was a member of the core development team for ADI’s baseband platform and direct conversion transceiver wireless product families and has been recipient of the company’s highest technical honor of ADI Fellow. 2008-2016 he was Senior Director and MediaTek Fellow leading the design of algorithms and architectures for cellular standards, as well as development of advanced technologies and product innovation strategies.