Report on Failure Resistant Interconnect Circuit with Time Based Decision Feedback Equalizer
On-chip serial links are attractive for high-speed point-to-point applications as they can achieve 10Gb/s or higher data rates without using power-hungry and floorplan-disrupting repeaters. Decision feedback equalization (DFE) has now become indispensable for improving the performance of off-chip links, however they have not been adopted widely in on-chip links due to the large power consumed by the current mode logic (CML) circuits required for high-speed operation. In an effort to make DFE more digital-friendly and amenable to technology scaling, we propose a time-based DFE technique where the weighted sum filter operation is performed entirely in the time domain. Our digital intensive approach utilizes inverters and digitally- controlled delay elements that can be readily designed in advanced technologies.