Session 6 - Integrated System Design II (TECHCON 2016)

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Home » Calendar » TECHCON 2016 » Session 6

Monday 12-Sep-2016 10:30 - 11:45 AM San Marcos
Session 6 - Integrated System Design II
6.1 10:30 AM STARnet
Ultra-Efficient Content Addressable Memory for Tunable GPU Approximation

Mohsen Imani (UC/San Diego)
6.2 10:45 AM STARnet
Performance Evaluation of Regular Expression Matching Engines Across Different Computer Architectures

Vinh Q. Dang (Univ. of Virginia)
6.3 11:00 AM STARnet
Near-Optimal Power Allocation on Arrays of Suboptimal Sensors

Noyan C. Sevuktekin (UIUC)
6.4 11:15 AM GRC
Prefetching Techniques for Near-memory Throughput Processors

Reena Panda (UT/Austin)
6.5 11:30 AM GRC
Understanding Latency Variation in Modern DRAM Chips: Experimental Characterization, Analysis, and Optimization

Kevin K. Chang (Carnegie Mellon Univ., Intel Fnd/SRCEA Fellow)

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