ABSTRACT
One of the (anonymous peer) reviewers of a recent paper from our group wrote that power-on ESD (e.g. powered IEC 61000-4-2) is a “hot topic” and evaluating chips under those conditions is becoming “increasingly common,” especially for automotive applications. That hot topic is the subject of this presentation.
Of particular concern is the case that a portion of the ESD current enters a chip IO pin. The presentation will begin with an examination of the paths by which ESD noise is transmitted from the IO supply to the other supplies on-chip. The noise amplitude is affected by the design of the ground distribution network and the integrated voltage regulators.
Latch-up is another consequence of power-on ESD. Reverse body bias is a technique used to place circuitry in a low-power (e.g., sleep) mode. For the NMOS transistors, there are two general approaches to generating the body bias: pump the P-wells to a lower potential than VSS, or ground the P-substrate and regulate the VSS bus voltage. We have identified that the latter approach may cause latch-up to occur during power-on ESD. The latch-up threshold is affected by the placement of the regulator’s pass transistor, the ESD protection network implementation, and the VSS net resistance.
Chips that are intended to survive some level of power-on ESD stress cannot utilize ESD protection circuitry that is inactivated when the power is on. Rail clamp circuits that provide protection against power-on ESD may also reduce the amplitude of supply noise due to simultaneous switching noise. The benefit gained depends on the frequency spectrum of the noise. Circuit simulation shows clearly the noise improvement from a well-designed rail clamp circuit but measuring the chip-level supply noise has proved to be challenging due to noise generated at the board-level. Time permitting, I will share details of the multiple board designs we have tested and solicited the attendees’ suggestions for our next re-spin.
BIO
Elyse Rosenbaum is the Melvin and Anne Louise Hassebrock Professor in Electrical and Computer Engineering at the University of Illinois at Urbana-Champaign. She received a Ph.D. degree in electrical engineering from the University of California, Berkeley. She is the director of the NSF-supported Center for Advanced Electronics through Machine Learning (CAEML), a joint project of the University of Illinois, Georgia Tech, and North Carolina State University. Her current research interests include machine-learning aided behavioral modeling of microelectronic components and systems, compact models, circuit reliability simulation, component, and system-level ESD reliability, and ESD-robust high-speed I/O circuit design.
Dr. Rosenbaum has authored or co-authored nearly 200 technical papers; she has been an editor for IEEE Transactions on Device and Materials Reliability and IEEE Transactions on Electron Devices. She was the recipient of a Best Student Paper Award from the IEDM, Outstanding, and Best Paper Awards from the EOS/ESD Symposium, a Technical Excellence Award from the SRC, an NSF CAREER award, an IBM Faculty Award, and the ESD Association’s Industry Pioneer Recognition Award. She is a Fellow of the IEEE.
