Grant Application for:
Device Sciences Program - Memory Technologies Research

Overview

The Device Sciences area is soliciting grant applications in the area of Memory Technologies.

This call for research, issued to universities worldwide, may be addressed by individual investigators or by research teams. Successful grant application submissions are expected to result in awards of unrestricted, non-overhead-bearing gifts. Near the conclusion of this 1-year research program, SRC may invite the funded research teams to offer proposals for a follow-on 3-year research contract to pursue reduction of the most important technical barriers to realizing the potential of the proposed approach. The number and size of the grants awarded will be determined by the amount of available funds and by the number of quality grant applications.

The funding amount or anticipated level of effort available for a solicited grant is intentionally not specified to allow a bidder flexibility to propose sufficient effort and resources to accomplish the objectives of this solicitation.

Research Needs

The 2003 edition of the International Technology Roadmap for Semiconductors (ITRS) anticipates emerging research devices for memory applications for the 32nm technology node that can be merged onto the CMOS technology platform. Many memory device concepts proposed to date have been demonstrated as a single bit memory cell but their viability for large-scale memory applications remains unclear. The majority of devices presented in a section of the ITRS entitled "Emerging Research Devices" have doubtful scalability to and beyond the 32nm technology node. Therefore, there is a need for high performance memory technology and architecture, exploiting parallelism, novel ideas to connect memory to a system, scalable beyond the 32nm node, while increasing the data clock rate.

Grant applications should offer new approaches for memory devices and circuits, providing high density, high performance, and low cost. We are also interested in the scaling principles related to conventional memory devices as well as for novel memory devices. Research components could include but should not be limited to new materials, new materials growth and fabrication technologies, novel memory devices and system architectural concepts.

Proposed novel memory devices may span a very broad range of materials and operational principles. Their potential use both for embedded or stand-alone applications is important. Of particular interest are memory devices suitable for 3-D integration, which can achieve the density of the 32nm technology node with relaxed lithographic features. There is also a special interest in novel thin film memory devices that could enable these devices to be applied to large-scale memory applications. For embedded applications, both memory devices and their sensing devices may be integrated in the back-end-of-the-line (BEOL) CMOS technology.

Topical areas of special interest include (but are not limited to) the following areas:

1. Innovative device or circuit solutions to enable SRAM scaling beyond the 32nm node with adequate noise margin.
2. Innovative device or circuit solutions to enable FLASH (including floating gate, NROM, and nanocrystals type) scaling beyond the 45nm node.
3. Fast, SRAM-like memory but with cell size better than 120F2 and minimal additional fabrication cost. (The cell size impacts not only the cost of the chip, but also the SRAM performance which is closely related to the interconnect delay of the memory block.)
4. Non-volatile memory (solid-state storage) that is scalable beyond the 32nm node.
5. Low temperature processing technology that enables the fabrication of active devices (transistors, diodes) at or below temperatures compatible with BEOL processes. The active devices should be adequate for performing address decoding, multiplexing for memory cells on 3-dimensionally integrated layers on top of CMOS circuits.
6. New memory technologies possessing a combination of attributes (read/write speed, retention, endurance, reliability etc.) that may open up new applications.

The grant application must describe the physical mechanism, scalability, stability, and propose sensing approaches if applicable. The grant application should also contain estimates of the eventual potential of the proposed approach based on simple, first order analysis. Architectural grant applications should clearly specify their novelty and potential benefits of the proposed approach. Further, the proposal should identify those most important technical/technology barriers to realizing the full potential of the proposed approach.

Grant Application Guidelines

Responses are limited to 4 pages (using at least a 10 pt. font) and must be submitted via the SRC Web site. Non-compliance with these guidelines will exclude grant applications from consideration.

Please include the following identifying information in your grant application:

• Project title
• Investigator(s)
• University
• Principal Author telephone number, mailing address, and e-mail address

Please make sure to address the following in your grant application:

• Background/context: emphasis area and problem to be addressed; describe why research is being done
• Objective: what you plan to accomplish in a 1-year exploratory program
• Rationale: value in terms of semiconductor industry needs
• Novelty: role of this research in advancing knowledge and state-of-the-art
• Approach: strategy for addressing the problem; describe important findings from your research to date
• Results: anticipated output of a successful effort
• Funding Request Amount: plan for 1-year program funded by an unrestricted, non-overhead bearing grant
• IP: identify any preexisting intellectual property

Timetable and Deadlines

Please direct all technical questions to Jim Hutchby, Director of Device Sciences (james.hutchby@src.org).
All other questions and responses should be directed to Jennifer Minor, (jennifer.minor@src.org, 919-941-9415).