Grant Application for:
Cross-disciplinary Semiconductor Research (CSR)


SRC is soliciting grant applications in Cross-disciplinary Semiconductor Research.

The goal of this initiative is to foster exploratory, multi-disciplinary, high-risk university research leading to novel high-payoff solutions for the science and technology challenges faced by the semiconductor industry at and beyond the time horizons of the International Technology Roadmap for Semiconductors (ITRS). Successful CSR projects will offer innovative and, hopefully, disruptive solutions to the challenge of enabling exponential gains in cost/performance benefits provided by the semiconductor industry for the foreseeable future, and may lead to novel applications for this industry.

This call for research, issued to universities worldwide, may be addressed by individual investigators or by research teams. The role of this program is to stimulate non-traditional thinking about the issues facing the semiconductor industry. It is intended to seed new research and programs for the SRC and MARCO. Consistent with the incubator role of the initiative, these awards will be 1 year, unrestricted, non-overhead bearing gifts with a funding level of $40K. Awardees are encouraged to develop a proposal for follow-on funding for expanded programs by the SRC, MARCO or other agencies. Follow-on SRC and MARCO funding will depend on the availability of funds and strategic plan alignment.


The scope of this solicitation is:

(1) Non-charge-based logic/memory devices

Challenge: Charge-based electronic devices will reach their fundamental limits in the foreseeable future, probably at or near the limits projected for 2020 by the 2005 International Technology Roadmap for Semiconductors. In charge-based logic at the extremes of scaling, there exist fundamental limits on size, speed, energy and error/noise immunity that force tradeoffs between density and speed of operation. In charge-based non-volatile memory, a similar problem is known as the voltage-time dilemma where higher voltages are required for faster speed of operation resulting in logic device mismatches, e.g. voltage and speed incompatibilities between logic and memory. Proposals are sought that:

  • provide smaller, faster, and less energetic binary switches, and
  • manage logic/memory mismatches

(2) Extremely scaled interconnect technologies/Interconnects for charge-based and alternative devices

Challenge: Copper interconnect technologies for CMOS chips are impacting system performance through increased power dissipation, signal delay, and cross-talk. Proposals are sought that:

  • Offer improved scaling performance for wire-based technologies that are compatible with CMOS technologies,
  • Characterize the fundamental scaling limits for wire-based interconnects, and
  • Describe interconnect technologies for non-charge based devices, e.g. spintronics, etc.

Grant Application Guidelines

Your response should address the planned research approach and possible research outcomes for the semiconductor industry. Responses are to be submitted as single PDF (or MS-Word) documents generated with 10 point or larger fonts. Limit document size to 3 pages sized to the US standard (8.5 by 11 inches). Non-compliance with these guidelines may exclude your grant application from consideration.

Please include the following identifying information on your grant application:

  • Project title
  • Investigator(s)
  • University
  • Telephone number, mailing address and e-mail address

Please address the following in your grant application:

  • Approximately 100 word executive summary
  • Problem to be addressed: explain the rationale for the project in terms of the semiconductor industry needs
  • Objective: what do you plan to do?
  • Novelty: the basic concept and discuss the role of cross-disciplinary research in providing a unique solution to the problem addressed
  • Approach: strategy for addressing the problem
  • Research output: identify possible research products of a successful research program
  • IP: identify preexisting intellectual property, if any

Timetable and Deadlines

Event Deadline
Deadline to Submit Grant Applications September 23, 2005
Notification of Final Program Selection Results November 16, 2005
Program/Funding Start December 1, 2005

Please direct all technical questions to Dr. Victor Zhirnov, (, 919-941-9454).
All other questions should be directed to Leslie Faiers, (, 919-941-9455).

4819 Emperor Blvd, Suite 300 Durham, NC 27703 Voice: (919) 941-9400 Fax: (919) 941-9450

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