White Paper for:
Semiconductor Device Compact Modeling for Circuit Design

Overview

SRC's Device Sciences area is soliciting white papers from a select set of universities for research directed to development of compact models of integrated semiconductor devices suitable for use in circuit design. Successful white paper authors will be invited to submit a full proposal. Contracts resulting from this solicitation are anticipated to be three years in duration.

The intent of this research is to aid SRC's member companies in their efforts to efficiently and accurately design digital, RF and analog integrated circuits using next generation single-gate (bulk and SOI) and multiple-gate non-classical semiconductor devices. Compact models resulting from this research should be capable of reproducing the device terminal behavior with accuracy, computational efficiency, ease of parameter extraction, and relative model simplicity for simulating a circuit or a system using current and future CMOS technology nodes. Models also should be capable of predictive simulation of circuits in the N+1 and N+2 technology nodes. This solicitation specifically addresses modeling device electrical characteristics related to digital (models for ultra thin oxide effects, leakage current, etc.) and mixed signal applications (models for noise, cross-talk effects, etc). The computational efficiency of any new model is important and should be addressed during model development, and effort should be made to improve computational efficiency where possible.

The research solicited is focused on three areas. The first area of research solicited relates to Extensions and Improvements to the PSP Compact Model. This work is intended to be performed by the Pennsylvania State University and should address the industry's need for a better model for RF and analog performance of MOSFETs. Numerous research topics need to be addressed to improve and extend the PSP model. Those with highest priority are: a) lateral non-uniform channel doping effects, e.g., in sub-threshold and on Rout; b) strained silicon, metal gate, and high K dielectric; c) proximity effects, e.g., stress/strain and well, as functions of layout; d) enhanced models for intrinsic and extrinsic parasitics, noise, and distributed effects; e) noise models scalable with geometry and voltage; and f) modeling of statistical fluctuations based on physical and geometric parameters.

The second area of high-priority research solicited is for development of a complete model for multiple gate structures as in Pi-FET, double-gate, FinFET, tri-gate etc. as discussed in the reference Compact Model Research Needs Document, February 20, 2006 Edition. For this second area of research, we solicit competitive White Papers from all universities receiving this solicitation.

The third area of high-priority research solicited relates to Extensions and Improvements to the BSIM4 and BSIMSOI Compact Models. This work is intended to be performed by the University of California - Berkeley and should address improving BSIM4 and BSIMSOI with noise models scalable with geometry and voltage.

Depending on the quality of proposals and the funds available, SRC may decide to pursue all, some or none of the proposed projects. SRC may also elect to negotiate a project's research scope or a team's composition to meet funding or synergy goals.

Research Needs

Additional information regarding technology barriers and prioritized research needs associated with this solicitation will be found in the document research needs document located below.

• Research Needs for CMOS Device Compact Modeling

White Paper Guidelines

Responses are to be submitted as single PDF (or MS-Word) documents generated with 10 point or larger fonts and must be submitted via the SRC Web site. Limit document size to three pages sized to the US standard (8.5 by 11 inches). Non-compliance with these guidelines may exclude your white paper from consideration.

Please include the following identifying information in your white paper:

• Project title
• Investigator(s)
• University(ies)
• Principal Author's telephone number, mailing address, and e-mail address

Please address the following topics in your white paper:

• Background/context: emphasis area and problem to be addressed; describe why research is being done
• Objective: what you plan to accomplish in a three-year program
• Rationale: value in terms of semiconductor industry needs
• Novelty: role of this research in advancing knowledge and state-of-the-art
• Approach: strategy for addressing the problem; describe important findings from your research to date
• Results: anticipated output of a successful effort
• Engagement: your plan for integration with SRC member companies
• Students: your plan for involvement and education of graduate students (a key SRC goal)
• Funding request: a per-year approximation of overall funding requirements (university approval and official budgets are not required at this time)
• IP: identify any pre-existing intellectual property

Awardees will be expected to:

• Disclose blocking background intellectual property
• Update information about participating students
• Submit publications resulting from sponsored research
• Participate in annual research reviews
• Provide annual reports and pre-defined deliverables

Timetable and Deadlines

Please direct all technical questions to Dr. Jim Hutchby, (james.hutchby@src.org ).
All other questions and responses should be directed to Jennifer Bennett, (jennifer.bennett@src.org).