Rescuing Uncorrectable Fault Patterns in On-chip Memories Through Error Pattern Transformation

  • Authors:
    Henry Duwe (UIUC), Xun Jian (UIUC), Rakesh Kumar (UIUC)
    Publication ID:
    Publication Type:
    Received Date:
    Last Edit Date:
    2385.001 (University of Illinois/Urbana-Champaign)


Voltage scaling can effectively reduce processor power, but reduces the reliability of SRAM cells in on-chip memories. To enable reliable memory operations at low voltages, many works propose using error correcting codes (ECCs). These ECCs must provide both high error coverage and low correction latency. Unfortunately, existing ECCs provide either low error coverage or high correction latency. We observe that the number of errors correctable by many low-latency ECCs differs widely depending on the error patterns of the protected words. We propose adaptively reordering the logical to physical bit mapping according to known fault patterns in the physical word. This reordering transforms many uncorrectable error patterns into correctable error patterns and, therefore, improves ECC error coverage. Our evaluations for an L1 cache show that applying our proposal to a low-latency ECC can tolerate 26.7x higher bit failure rate than the best low-latency ECC baseline alone with no additional cycles.

Past Events

  Event Summary
20–22 September 2015
Sunday, Sept. 20, 2015, 8 a.m. — Tuesday, Sept. 22, 2015, 10 p.m. CT
Austin, TX, United States
Technical conference and networking event for SRC members and students.

4819 Emperor Blvd, Suite 300 Durham, NC 27703 Voice: (919) 941-9400 Fax: (919) 941-9450

Important Information for the SRC website. This site uses cookies to store information on your computer. By continuing to use our site, you consent to our cookies. If you are not happy with the use of these cookies, please review our Cookie Policy to learn how they can be disabled. By disabling cookies, some features of the site will not work.