RAPID: Accelerating Pattern Search Applications with Reconfigurable Hardware
Recent research has demonstrated the efficacy of accelerating textual pattern search tasks using specialized hardware, such as Micron's Automata Processor (AP) and FPGAs, but programming these devices is often challenging for non-hardware-experts. To address this, we present RAPID, a high-level programming language and combined imperative and declarative model for programming pattern-recognition processors. RAPID is clear, maintainable, concise, and efficient both at compile and run time. We discuss the tools and algorithms we have developed and evaluate a suite of RAPID programs against custom, baseline implementations previously demonstrated to be significantly accelerated by specialized hardware. We show that RAPID programs are much shorter in length, are expressible at a higher level of abstraction than their handcrafted counterparts, and yield generated code that is often more compact.
Sunday, Sept. 11, 2016, 8 a.m. — Tuesday, Sept. 13, 2016, 10 p.m. CT
Austin, TX, United States
Technical conference and networking event for SRC members and students.