RAPID: Accelerating Pattern Search Applications with Reconfigurable Hardware

  • Authors:
    Kevin Angstadt (Univ. of Virginia), John Wadden (Univ. of Virginia), Xiaoping Huang (Northwestern Polytechnic), Mohamed El-Hadedy (UIUC), Westley Weimer (Univ. of Virginia), Kevin Skadron (Univ. of Virginia)
    Publication ID:
    P088285
    Publication Type:
    Paper
    Received Date:
    12-Jul-2016
    Last Edit Date:
    13-Jul-2016
    Research:
    2384.007 (University of Michigan)

Abstract

Recent research has demonstrated the efficacy of accelerating textual pattern search tasks using specialized hardware, such as Micron's Automata Processor (AP) and FPGAs, but programming these devices is often challenging for non-hardware-experts. To address this, we present RAPID, a high-level programming language and combined imperative and declarative model for programming pattern-recognition processors. RAPID is clear, maintainable, concise, and efficient both at compile and run time. We discuss the tools and algorithms we have developed and evaluate a suite of RAPID programs against custom, baseline implementations previously demonstrated to be significantly accelerated by specialized hardware. We show that RAPID programs are much shorter in length, are expressible at a higher level of abstraction than their handcrafted counterparts, and yield generated code that is often more compact.

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