Optimization of 2D nTFET and pTFET Based AlSb/GaSb/InAs/In(x)Al(1-x)As(x)Sb(1-x) Grown on InAs Substrate Structure with Ballistic Simulations in Full Tight Binding Space

  • Authors:
    Mykhailo Povolotskyi (Purdue)
    Publication ID:
    P090168
    Publication Type:
    Deliverable Report
    Received Date:
    31-Jan-2017
    Last Edit Date:
    9-May-2017
    Research:
    2694.003 (Purdue University)

Research Report Highlight

Simulations of a new tunnel FET design based on AlSb/GaSb/InAs/InAlAsSb heterostructure show, that a 15nm-gate TFET (both n-type and p-type) can achieve 500A/m ON-current at 0.3 V with 0.001A/m OFF-current, which is 10x improvement in TFET performance.

Abstract

Transistor design optimization based on AlSb/GaSb/InAs/In(x)Al(1-x)As(x)Sb(1-x) structure grown on InAs substrate is reported. 2D designs (FinFET geometry) for n-type and p-type TFETs are considered. The ballistic simulations show, that by using a triple heterostructure design with the gate length of 15nm, both n-type and p-type TFETs can achieve about 500A/m ON-current at 0.3 applied bias with 0.001A/m OFF-current, which is more than ten times improvement over conventional heterostructure TFET design. In addition, the triple heterostructure design removes a sub-linear character in transient IV characteristics of a p-type TFET.

4819 Emperor Blvd, Suite 300 Durham, NC 27703 Voice: (919) 941-9400 Fax: (919) 941-9450