Hardware Security and Trust: Evolution of Logic Locking
Globalization of Integrated Circuit (IC) design and manufacturing is making designers and users of ICs re-assess their trust in hardware. As the IC design flow spans the globe - driven by cost-conscious consumer electronics - hardware is increasingly prone to reverse engineering, Intellectual Property (IP) piracy and malicious modifications (i.e., hardware trojans). An attacker, anywhere within the global design flow, can reverse engineer the functionality of an IC/IP, steal and claim ownership of the IP or introduce counterfeits into the supply chain. Moreover, an untrusted IC fab may overbuild ICs and sell them illegally. Finally, rogue elements in the fabs may insert hardware trojans into the design without the knowledge of the designer or the end-user of the IC; this additional functionality may subsequently be exploited to introduce errors in the results, steal sensitive information or incapacitate a fielded system. The semiconductor industry routinely loses billions annually due to these attacks.
This workshop will cover various forms of threats that the electronic chip supply chain is up against as well as defenses against these threats. It will elucidate the development of CAD algorithms/tools for this newly emerging field by mostly leveraging principles from other more mature research domains. The workshop will show that designers can regain control over the distributed design and manufacturing flow by acting more proactively in building on-chip defenses to protect their design. In particular, the “design-for-trust” techniques to be covered are various versions of logic locking; the workshop will elucidate the evolution of logic locking techniques, including the early efforts in logic locking (task funded by SRC) as well the most recent ones.
|Hardware Security and Trust: Evolution of Logic Locking|
Friday, Feb. 24, 2017, 1 p.m.–2 p.m. ET
Durham, NC, United States