Final Report on Design and Automation of a Novel Low Swing Clocking Methodology with Reduced Delay Uncertainty

  • Authors:
    Emre Salman (Stony Brook), Baris Taskin (Drexel Univ.)
    Publication ID:
    Publication Type:
    Deliverable Report
    Received Date:
    Last Edit Date:
    2449.001 (Stony Brook University - SUNY)
    2450.001 (Drexel University)

Research Report Highlight

A low voltage swing clocking methodolgy using both circuit and algorithmic innovations has been used to obtain a 42% reduction in clock power. The methodology included both a novel low power, low voltage flip-flop and a skew aware clock tree synthesis.


A low voltage/swing clocking methodology has been developed through both circuit and algorithmic innovations. The primary objective is to significantly reduce the power consumed by the clock network while maintaining the circuit performance (clock frequency and clock constraints on skew and slew) the same. The methodology consists of two primary components: 1) a novel D-flip-flop (DFF) cell that maximizes power savings by enabling low voltage/swing operation throughout the entire clock network and 2) a novel slew-aware clock tree synthesis (CTS) algorithm to ensure that the same timing constraints (i.e. clock frequency, skew, and slew) are satisfied despite the low operating voltage. A useful skew methodology has also been introduced to mitigate timing degradations (due to reduced clock voltage) along the Enable paths of integrated clock gating cells (ICGs). The proposed methodology is integrated within an industrial design flow. Experimental results have been obtained for 45 nm and 32 nm bulk CMOS technologies, 20 nm FinFET technology, and a 16 nm industrial FinFET technology. In bulk CMOS technology, up to 44% reduction in clock power and 32% reduction in flip-flop power has been achieved at 1 GHz clock frequency, while satisfying the same timing constraints. In FinFET technologies, an overall (clock network + flip-flop) 42% reduction in power consumption has been achieved at 3 GHz clock frequency. Experimental results on industrial circuits demonstrate that the proposed methodology outperform existing clock tree synthesis tools in generating a low voltage clock distribution network. Technology transfer to industry has been achieved through several internships. The proposed flip-flop is implemented within a test chip to obtain measurement results and integration into the cell library. The primary future step of this research is to develop a low voltage and variation aware clock tree synthesis methodology. The objective is to generate a "correct by design" clock network for variations (rather than post-CTS optimization), thereby reducing significant pessimism while ensuring a reliable low voltage clock operation in the presence of variations.

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