Incorporating Graphene into Back End-of-Line for Better Cu Interconnects
Cu interconnects with low-k dielectric have scaled concomitantly with transistor for two decades. However, further interconnects scaling is constrained by the escalating RC delay and Cu electromigration (EM) reliability problems. For sub-80 nm wire pitch, the problems are exacerbated due to the increasing Cu wire resistivity, thick diffusion barrier occupying larger portion of the conduction area, and higher current density stressing the EM lifetime. On the other hand, graphene provides possibly the thinnest and highly conductive barrier and capping layer, and thus extends further scaling of Cu interconnects. In this talk, we’ll discuss advantages and challenges of employing graphene as the barrier and the capping layer for ultimate scaled Cu wire. System simulation predicts an 8% speed boost or 12% energy conservation and higher tolerance for variations with the use of graphene diffusion barrier. Benchmarked with industrial standard materials, 3 Å single-layer graphene provides 3.3× longer barrier lifetime than 2 nm TaN and 10× better electromigration lifetime than 2 nm CoWP. SiNx capping is additionally investigated. Graphene defects including grain boundaries and transfer induced defects are the main Cu diffusion path. Thus better performance is expected with higher quality and less defected graphene. Low-temperature direct CVD grown graphene on Cu wire provides a back end-of-line compatible process. Pristine interface between graphene and Cu enables extra binding for Cu atoms and thus results in enhanced EM performances. However, highly defective graphene from the low-temperature growth still needs improvement for better performances.
|Incorporating Graphene into Back End-of-Line for better Cu Interconnects|
Wednesday, April 26, 2017, 11 a.m.–noon PT
Los Angeles, CA, United States