A Pathway to Enable Exponential Scaling for the Beyond-CMOS Era

  • Authors:
    Sachin S. Sapatnekar (Univ. of Minnesota), Jian-Ping Wang (Univ. of Minnesota), Chris H. Kim (Univ. of Minnesota), Paul Crowell (Univ. of Minnesota), Steven Koester (Univ. of Minnesota), Supriyo Datta (Purdue), Kaushik Roy (Purdue), Anand Raghunathan (Purdue), Xiaobo Sharon Hu (Univ. of Notre Dame), Michael T. Niemier (Univ. of Notre Dame), Azad J. Naeemi (Georgia Tech), Chia-Ling Chien (Johns Hopkins), Caroline Ross (MIT), Roland Kawakami (Ohio State)
    Publication ID:
    Publication Type:
    Received Date:
    Last Edit Date:
    2381.001 (Johns Hopkins University)
    2381.004 (University of Minnesota)
    2381.005 (Purdue University)
    2381.006 (University of Minnesota)


Many key technologies of our society, including so-called artificial intelligence (AI) and big data, have been enabled by the invention of transistor and its ever-decreasing size and ever-increasing integration at a large scale. However, conventional technologies are confronted with a clear scaling limit. Many recently proposed advanced transistor concepts are also facing an uphill battle in the lab because of necessary performance tradeoffs and limited scaling potential. We argue for a new pathway that could enable exponential scaling for multiple generations. This pathway involves layering multiple technologies that enable new functions beyond those available from conventional and newly proposed transistors. The key principles for this new pathway have been demonstrated through an interdisciplinary team effort at C-SPIN (a STARnet center), where systems designers, device builders, materials scientists and physicists have all worked under one umbrella to overcome key technology barriers. This paper reviews several successful outcomes from this effort on topics such as the spin memory, logic-in-memory, cognitive computing, stochastic and probabilistic computing and reconfigurable information processing.

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