Automated Cross-level Validation and Debug of Mixed-signal Systems in Top-down Design: From Pre-silicon to Post-silicon

  • Authors:
    Abhijit Chatterjee (Georgia Tech), Barry J. Muldrey (Georgia Tech), Sabyasachi Deyati (Georgia Tech)
    Publication ID:
    P090837
    Publication Type:
    Annual Review
    Received Date:
    8-May-2017
    Last Edit Date:
    8-May-2017
    Research:
    2712.005 (Georgia Institute of Technology)

Abstract

In top-down design, the models for mixed-signal functions are first specified at the behavioral level using, for example, Simulink, MATLAB, Verilog-AMS or A-VHDL. The design is then refined using more detailed macro-block models, that evolve to transistor level models and eventually silicon. At each stage of design refinement, it is necessary to establish equivalence between behaviors across different design levels including fabricated silicon. If discrepancies are detected, they need to be debugged immediately. However, pre-silicon through post-silicon validation of mixed-signal circuits and systems remains primitive compared to the state of the art for digital systems. AMS heterogeneity in modern SoCs is steadily increasing and the number of bug escapes to silicon has increased significantly over the last decade. Data from Mentor Graphics suggests as many as 6-7 respins for “difficult” SoC designs. Most companies today have a brute-force manually intensive approach to mixed-signal validation. Comprehensive solutions to the mixed-signal validation problem do not exist today and are executed largely manually with little automation. The intent of this research is to provide automated tools that make debugging of complex mixed-signal SoCs orders of magnitude easier while providing guidance for quick circuit redesign to minimize the number of silicon respins.

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15–16 May 2017
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Monday, May 15, 2017, 1 p.m. — Tuesday, May 16, 2017, 2 p.m. ET
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