A 74.33 dB SNDR 20 MSPS 2.74 mW Pipelined ADC using a Dynamic Deadzone Ring Amplifier

  • Authors:
    Spencer D. Leuenberger (Oregon State Univ.), Jason R. Muhlestein (Intel), Hyuk Sun (Oregon State Univ.), Praveen Venkatachala (Oregon State Univ.), Un-Ku Moon (Oregon State Univ.)
    Publication ID:
    Publication Type:
    Received Date:
    Last Edit Date:
    2712.010 (Oregon State University)


Ring amplifiers have emerged as a scalable amplification technique. This work is a ring amplifier built with current-starved inverters in the intermediate stage. This structure allows for the implementation of a dynamic deadzone that allows a single amplifier to perform both coarse estimation and fine settling. A pipelined ADC with a sampling speed of 20 MSPS is implemented in 0.18um CMOS. The ADC consumes 2.74 mW and achieves a peak SNDR of 74.33 dB which provides a FoM of 32.2 fJ/c-step with no calibration required.

4819 Emperor Blvd, Suite 300 Durham, NC 27703 Voice: (919) 941-9400 Fax: (919) 941-9450

Important Information for the SRC website. This site uses cookies to store information on your computer. By continuing to use our site, you consent to our cookies. If you are not happy with the use of these cookies, please review our Cookie Policy to learn how they can be disabled. By disabling cookies, some features of the site will not work.