A 74.33 dB SNDR 20 MSPS 2.74 mW Pipelined ADC using a Dynamic Deadzone Ring Amplifier

  • Authors:
    Spencer D. Leuenberger (Oregon State Univ.), Jason R. Muhlestein (Intel), Hyuk Sun (Oregon State Univ.), Praveen Venkatachala (Oregon State Univ.), Un-Ku Moon (Oregon State Univ.)
    Publication ID:
    P091225
    Publication Type:
    Paper
    Received Date:
    30-Jun-2017
    Last Edit Date:
    10-Jul-2017
    Research:
    2712.010 (Oregon State University)

Abstract

Ring amplifiers have emerged as a scalable amplification technique. This work is a ring amplifier built with current-starved inverters in the intermediate stage. This structure allows for the implementation of a dynamic deadzone that allows a single amplifier to perform both coarse estimation and fine settling. A pipelined ADC with a sampling speed of 20 MSPS is implemented in 0.18um CMOS. The ADC consumes 2.74 mW and achieves a peak SNDR of 74.33 dB which provides a FoM of 32.2 fJ/c-step with no calibration required.

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