Compact Model for Spin-transfer-torque Magnetic Tunnel Junction Device
In this work, we describe a compact model designed for Spin-transfer-torque (STT) RAM device developed in Verilog-A. The model is computationally simple and successfully captures all the high level behavior of memory switching such as programming and read voltages, currents and pulse time-scales. We make use of the Landau-Lifshitz-Gilbert-Slonczewski (LLGS) equation that evaluates the transient behavior of the magnetization vector (M). STT-RAM devices are known have inherent stochasticity in their switching characteristics. Our contribution to this work is introducing stochastic state change into an existing LLGS based STT-RAM model. This holds potential for implementing stochastic synapses for different neural network architectures.