Low Power Area Efficient Flexible-rate Energy Proportional Serial Link Transceivers

  • Authors:
    Dongwook Kim (UIUC), Pavan Kumar Hanumolu (UIUC)
    Publication ID:
    Publication Type:
    Annual Review
    Received Date:
    Last Edit Date:
    2712.009 (University of Illinois/Urbana-Champaign)


Clock generation, recovery, and distribution consumes significant power in high speed interfaces. A sub-baud-rate CDR that can recovery clock and data using only single quarter-rate clock is presented. Using two samplers and two current integrators four data bits are recovered in each clock cycle. Fabricated in a 65nm CMOS process, the prototype CDR recovers 15.2Gb/s data using a single 3.8GHz clock and achieves BER < 10-12, > 10MHz JTOL corner, 537fsrms recovered clock jitter, and 1.9pJ/bit energy efficiency.

Past Events

  Event Summary
17–19 October 2017
Texas Analog Center of Excellence and Analog/Mixed-Signal Circuits, Systems and Devices Review
Tuesday, Oct. 17, 2017, 8 a.m. — Thursday, Oct. 19, 2017, noon CT
Richardson, TX, United States

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