The Pennsylvania State University research teams of Suman Datta and Vijay Narayanan have collaborated in the design of a III-V HTFET successive-approximation-register (SAR) analog-to-digital converter (ADC). Benchmarking of the HTFET-based 6-bit SAR ADC shows its promising energy efficiency compared to the 20 nm Si FinFET design. The 6-bit 10-MS/s HTFET SAR ADC achieves a figure of merit of 1.08 fJ/conversion-step, effective number of bits of 5.14, with power consumption of 0.38 μW at 0.3 V.