RESEARCH TRIANGLE PARK, N.C. - Semiconductor Research Corporation (SRC), the world's leading university-research consortium for semiconductors and related technologies, today announced that the College of Nanoscale Science and Engineering (CNSE) of the University at Albany will serve as headquarters for a comprehensive research effort aimed at enabling nanoelectronics advances that are critical for the development of smaller, faster and cheaper computer nanochips amid the approaching limits of interconnect scaling.

The $7.5 million, three-year program, which is funded jointly by SRC and New York State, begins this month, with the UAlbany NanoCollege serving as home for the New York Center for Advanced Interconnect Science and Technology (NY CAIST). In addition to CNSE, universities contributing to the research results will be Columbia University, Cornell University, Lehigh University, Massachusetts Institute of Technology (MIT), Penn State, Rensselaer Polytechnic Institute (RPI), Stanford, SUNY Binghamton, University of Florida, University of Maryland, University of North Texas, University of Texas at Arlington and the University of Texas at Austin.

Interconnect scaling is one of the key enablers for the continuation of the aggressive pace for increasing the functionality of chips, known as Moore's Law, beyond 2011. As part of the NY CAIST program, 27 new research projects are planned, aimed at extending copper and low-k dielectric scaling that will ultimately serve chipmakers and end-users for communications, computing, gaming, automotive and consumer electronics, and a wide range of other applications that are dependent on silicon's performance.

"Since interconnect performance is starting to dominate chip performance more than devices do, interconnect research is increasingly important to ensure continued scaling of semiconductors," said Scott List, an Intel assignee who is director of interconnect and packaging research at Global Research Collaboration (GRC), a unit of the SRC that is responsible for narrowing the options for carrying CMOS to its ultimate limit. "Interconnect scaling is fully half the solution for technology required to drive chip geometries beyond 22 nanometers. As we evaluate options like carbon nanotubes and optical interconnects, we've found there are few viable interconnect choices for implementation at 22-nm. It's vital that we continue to build upon the progress we've made with NY CAIST toward copper and low-k scaling."

"Working in collaboration with the Semiconductor Research Corporation and our esteemed colleagues from the nation's preeminent research universities, the UAlbany NanoCollege is pleased to lead this important endeavor designed to enable vital progress at the nanoscale that is essential to advancing the industry's science and technology roadmap and serving the needs of the international leading computer chip companies," said Dr. Alain E. Kaloyeros, Vice President and Chief Administrative Officer at CNSE. "To this end, the New York CAIST has assembled a critical mass of innovative research projects to explore monolithic and hybrid electrical and optical interconnect solutions that hold tremendous promise for emerging nanoscale chip technologies."

Every year, through the industry's collective efforts, switching speeds on chips have grown nearly 20 percent faster with a 30 percent wire and transistor density increase. However, the ability to continue this pace will eventually slow down without implementation of new interconnect materials, processes, metrology and concepts.

The NY CAIST will be managed by an executive team headed by Professor Alain E. Kaloyeros, Vice President and Chief Administrative Officer of the UAlbany CNSE, who will serve as principal investigator. Professor Eric Lifshin of UAlbany and Professor Alan C. West of Columbia will serve as, respectively, technical director and technical co-director and will coordinate the development and execution of the various technical thrusts of the CAIST.

To accomplish the research, SRC and the NY CAIST at CNSE will direct cross-functional collaboration of researchers under one roof for coordination of projects in the following areas:

• Reduction of the sidewall and grain boundary scattering to decrease copper (Cu) resistivity at sub-40nm dimensions,
• Development of a new class of Cu diffusion barriers with thicknesses of a few atoms,
• Development of metrology to measure buried interfaces with atomic resolution,
• Optimization of the size and structure of voids in low-k dielectrics on the scale of a few atoms to increase speed while maintaining strength,
• Understanding the fundamental failure mechanisms in interconnects to reduce shorts in the dielectrics and opens in the Cu wires.

The research will enhance work conducted at NY CAIST over the past three years by SRC, GRC and its academic partners. Previous results include the demonstration of 50 percent reduction in the sidewall scattering from the edges of the Cu wires, sub-ten-atom thick diffusion barriers and evaluation of novel optical and carbon nanotube-based interconnects.

The 22nm node is projected by the International Technology Roadmap for Semiconductors (ITRS) to be implemented in commercial production by 2011-12. Per its charter, SRC-GRC will continue to take a lead role in collaborating on enhancements to the academic research agenda for materials and processes associated with semiconductor manufacturing.

About SRC
Celebrating 26 years of collaborative research for the semiconductor industry, SRC defines industry needs, invests in and manages the research that gives its members a competitive advantage in the dynamic global marketplace. Awarded the National Medal of Technology, America's highest recognition for contributions to technology, SRC expands the industry knowledge base and attracts premier students to help innovate and transfer semiconductor technology to the commercial industry. Based in Research Triangle Park, NC, SRC's GRC program drives long-term semiconductor research contracts on behalf of its participating members: Advanced Micro Devices, Inc., Applied Materials, Inc., Axcelis Technologies, Inc., Cadence Design Systems, Freescale Semiconductor, Inc., Hewlett-Packard Co., IBM Corp., Intel Corp., LSI Logic Corp., Mentor Graphics Corp., The Mitre Corp., Novellus Systems, Inc., Rohm and Haas Electronic Materials, Texas Instruments Corp. and Tokyo Electron Ltd. SRC also seeks to leverage funding from global government agencies. For more information, visit www.src.org.

About CNSE
The UAlbany CNSE is the first college in the world dedicated to research, development, education, and deployment in the emerging disciplines of nanoscience, nanoengineering, nanobioscience, and nanoeconomics. In May 2007, it was ranked as the world's number one college for nanotechnology and microtechnology in the Annual College Ranking by Small Times magazine. CNSE's Albany NanoTech complex is the most advanced research facility of its kind at any university in the world: a $4.2 billion, 450,000-square-foot complex that attracts corporate partners from around the world and offers students a one-of-a-kind academic experience. The UAlbany NanoCollege houses the only fully-integrated, 300mm wafer, computer chip pilot prototyping and demonstration line within 65,000 square feet of Class 1 capable cleanrooms. More than 2,000 scientists, researchers, engineers, students, and faculty work on site at CNSE's Albany NanoTech complex, from companies including IBM, AMD, SONY, Toshiba, ASML, Applied Materials, Tokyo Electron, and Freescale. An expansion currently underway will increase the size of CNSE's Albany NanoTech complex to over 800,000 square feet, including over 80,000 square feet of Class 1 capable cleanroom space, to house over 2,500 scientists, researchers, engineers, students, and faculty by mid-2009. For more information, visit www.cnse.albany.edu/index.cfm.

SRC media contact

Steve Janack
College of Nanoscale Science and Engineering
sjanack@uamail.albany.edu
(518) 956-7322
(518) 312-5009 (cell)