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1 through 30 of 332 similar documents, best matches first.   
Results by:Thunderstone Page: 1 2 3 4 5 6 7 8 9 10 next >>
1: Method and Architecture for Pre-bond Probing of TSVs in 3D Stacked...
Method and Architecture for Pre-bond Probing of TSVs in 3D Stacked Integrated Circuits Application Type: Utility Patent Number: 8775108 Country: United States Status: Filed on ...
URL: https://www.src.org/library/patent/p1291/
Modified: 2014-07-08 - 22KB
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2: Multi-Layer Integrated Circuits Having Isolation Cells for Layer...
Multi-Layer Integrated Circuits Having Isolation Cells for Layer Testing and Related Methods Application Type: Continuation (in part) Patent Number: 10838003 Country: United States ...
URL: https://www.src.org/library/patent/p1826/
Modified: 2020-11-17 - 25KB
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3: Multi-Layer Integrated Circuits Having Isolation Cells for Layer...
Multi-Layer Integrated Circuits Having Isolation Cells for Layer Testing and Related Methods Application Type: Utility Patent Number: 10338133 Country: United States Status: Filed ...
URL: https://www.src.org/library/patent/p1639/
Modified: 2019-07-02 - 25KB
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4: Non-Invasive Pre-Bond TSV TestUsing Ring Oscillators and Multiple...
Non-Invasive Pre-Bond TSV TestUsing Ring Oscillators and Multiple Voltage Levels Application Type: Utility Patent Number: 9478720 Country: United States Status: Filed on ...
URL: https://www.src.org/library/patent/p1392/
Modified: 2016-11-01 - 24KB
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5: Non-Invasive Pre-Bond TSV Test using Ring Oscillators and Multiple...
Non-Invasive Pre-Bond TSV Test using Ring Oscillators and Multiple Voltage Levels Application Type: Continuation Patent Number: 10444279 Country: United States Status: Filed on ...
URL: https://www.src.org/library/patent/p1635/
Modified: 2019-10-15 - 23KB
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6: Scan Test of Die Logic in 3D ICs Using TSV Probing (Patent P1368...
Scan Test of Die Logic in 3D ICs Using TSV Probing Application Type: Utility Patent Number: 8782479 Country: United States Status: Filed on 1-Nov-2012, Issued on 15-Jul-2014, ...
URL: https://www.src.org/library/patent/p1368/
Modified: 2014-07-15 - 22KB
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7: Power Switch Design and Method for Reducing Leakage Power in...
Power Switch Design and Method for Reducing Leakage Power in Low-Power Integrated Circuits Application Type: Utility Patent Number: 8373493 Country: United States Status: Filed on ...
URL: https://www.src.org/library/patent/p1239/
Modified: 2013-02-12 - 22KB
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8: Testing Monolithic Three Dimensional Integrated Circuits (Patent...
Testing Monolithic Three Dimensional Integrated Circuits Application Type: Utility Patent Number: 10775429 Country: United States Status: Filed on 2-Nov-2017, Issued on 15-Sep-2020 ...
URL: https://www.src.org/library/patent/p1746/
Modified: 2020-09-15 - 25KB
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9: Software-Based Self-Test and Diagnosis Using on-Chip Memory ...
Software-Based Self-Test and Diagnosis Using on-Chip Memory Application Type: Divisional Patent Number: 10788532 Country: United States Status: Filed on 30-Nov-2017, Issued on ...
URL: https://www.src.org/library/patent/p1753/
Modified: 2020-09-29 - 26KB
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10: Software-Based Self-Test and Diagnosis Using on-Chip Memory ...
Software-Based Self-Test and Diagnosis Using on-Chip Memory Application Type: Divisional Patent Number: 10845416 Country: United States Status: Filed on 30-Nov-2017, Issued on ...
URL: https://www.src.org/library/patent/p1752/
Modified: 2020-11-24 - 26KB
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11: Software-Based Self-Test and Diagnosis Using On-Chip Memory ...
Software-Based Self-Test and Diagnosis Using On-Chip Memory Application Type: Utility Patent Number: 9864007 Country: United States Status: Filed on 30-Apr-2014, Issued on ...
URL: https://www.src.org/library/patent/p1457/
Modified: 2018-01-09 - 25KB
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12: Signal Tracing Using On-Chip Memory For In-System Post-Fabrication...
Signal Tracing Using On-Chip Memory For In-System Post-Fabrication Debug Application Type: Utility Patent Number: 9720036 Country: United States Status: Filed on 18-Aug-2014, ...
URL: https://www.src.org/library/patent/p1495/
Modified: 2017-08-01 - 23KB
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13: Signal Tracing using ON-Chip Memory for In-System Post-Fabrication...
Signal Tracing using ON-Chip Memory for In-System Post-Fabrication Debug Application Type: Continuation Patent Number: 10732221 Country: United States Status: Filed on 26-Jun-2017, ...
URL: https://www.src.org/library/patent/p1733/
Modified: 2020-08-04 - 24KB
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14: Retiming-Based Design Flow for Delay Recovery on Inter-Die Paths...
Retiming-Based Design Flow for Delay Recovery on Inter-Die Paths in 3D ICs Application Type: Utility Patent Number: 8832608 Country: United States Status: Filed on 17-Jun-2013, ...
URL: https://www.src.org/library/patent/p1411/
Modified: 2014-09-09 - 22KB
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15: Evaluating Functional Fault Criticality of Structural Faults...
Evaluating Functional Fault Criticality of Structural Faults for Circuit Testing Application Type: Utility Patent Number: 12008298 Country: United States Status: Filed on ...
URL: https://www.src.org/library/patent/p1929/
Modified: 2024-06-11 - 29KB
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16: Fault Criticality Assessment using Graph Convolutional Networks...
Fault Criticality Assessment using Graph Convolutional Networks Application Type: Utility Country: United States Status: Filed on 29-Jan-2021, Published by Patent Office ...
URL: https://www.src.org/library/patent/p1956/
Modified: 2021-01-29 - 22KB
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17: Securing Heterogeneous 2.5D ICs Against IP Theft Through Dynamic...
Securing Heterogeneous 2.5D ICs Against IP Theft Through Dynamic Interposer Obfuscation Application Type: Provisional Country: United States Status: Filed on 22-Dec-2022, Patent ...
URL: https://www.src.org/library/patent/p2108/
Modified: 2022-12-22 - 23KB
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18: Method and Circuit for Reducing Leakage and Increasing Read Stability...
Method and Circuit for Reducing Leakage and Increasing Read Stability in a Memory Device Application Type: Utility Patent Number: 7328413 Country: United States Status: Filed on ...
URL: https://www.src.org/library/patent/p0486/
Modified: 2008-02-05 - 22KB
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19: Architecture and Method for Real-Time Parallel Detection and...
Architecture and Method for Real-Time Parallel Detection and Extraction of Maximally Stable Extremal Regions (MSERs) Application Type: Utility Patent Number: 9311555 Country: ...
URL: https://www.src.org/library/patent/p1493/
Modified: 2016-04-12 - 22KB
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20: ARCHITECTURE AND METHOD FOR MAXIMALLY STABLE EXTREMAL REGIONS...
ARCHITECTURE AND METHOD FOR MAXIMALLY STABLE EXTREMAL REGIONS (MSERs)-BASED EXUDATES DETECTION IN FUNDUS IMAGES FOR DIABETIC RETINOPATHY Application Type: Utility Patent Number: ...
URL: https://www.src.org/library/patent/p1596/
Modified: 2019-10-29 - 22KB
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21: Interconnection Architecture and Method of Assessing Interconnection...
Interconnection Architecture and Method of Assessing Interconnection Architecture Application Type: Utility Patent Number: 7622779 Country: United States Status: Filed on ...
URL: https://www.src.org/library/patent/p1027/
Modified: 2009-11-24 - 23KB
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22: Integrated Circuit Implementation of Methods and Apparatuses...
Integrated Circuit Implementation of Methods and Apparatuses for Monitoring Occupancy of Wideband GHz Spectrum, and Sensing Respective Frequency Components of Time-Varying Signals ...
URL: https://www.src.org/library/patent/p1542/
Modified: 2016-04-02 - 26KB
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23: Integrated Circuit Implementation of Methods and Apparatuses...
Integrated Circuit Implementation of Methods and Apparatuses for Monitoring Occupancy of Wideband GHz Spectrum, and Sensing Respective Frequency Components of Time-Varying Signals ...
URL: https://www.src.org/library/patent/p1543/
Modified: 2014-11-19 - 26KB
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24: Methods of Generating Integrated Circuit (IC) Layout Synthetic...
Methods of Generating Integrated Circuit (IC) Layout Synthetic Patterns and Related Computer Program Products Application Type: Utility Patent Number: 11449658 Country: United ...
URL: https://www.src.org/library/patent/p1862/
Modified: 2022-09-20 - 24KB
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25: System and Method to Test Integrated Circuits on a Wafer (Patent...
System and Method to Test Integrated Circuits on a Wafer Application Type: Utility Patent Number: 7325180 Country: United States Status: Filed on 26-Nov-2003, Issued on ...
URL: https://www.src.org/library/patent/p0413/
Modified: 2008-01-29 - 22KB
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26: Method for Diagnosing Bridging Faults in Integrated Circuits...
Method for Diagnosing Bridging Faults in Integrated Circuits Application Type: Utility Patent Number: 6202181 Country: United States Status: Filed on 3-Nov-1997, Issued on ...
URL: https://www.src.org/library/patent/p0199/
Modified: 2001-03-13 - 23KB
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27: Method and System for Synthesizing Relative Timing Constraints...
Method and System for Synthesizing Relative Timing Constraints on an Integrated Circuit Design to Facilitate Timing Verification Application Type: Continuation Patent Number: ...
URL: https://www.src.org/library/patent/p1354/
Modified: 2012-11-27 - 24KB
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28: Method and System for Synthesizing Relative Timing Constraints...
Method and System for Synthesizing Relative Timing Constraints on an Integrated Circuit Design to Facilitate Timing Verification Application Type: Utility Patent Number: 8239796 ...
URL: https://www.src.org/library/patent/p1202/
Modified: 2012-08-07 - 24KB
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29: Method for Diagnosing Bridging Faults in Integrated Circuits...
Method for Diagnosing Bridging Faults in Integrated Circuits Application Type: Continuation (in part) Patent Number: 6560736 Country: United States Status: Filed on 10-Jan-2001, ...
URL: https://www.src.org/library/patent/p0338/
Modified: 2003-05-06 - 23KB
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30: Multiple Copper Vias for Integrated Circuit Metallization and...
Multiple Copper Vias for Integrated Circuit Metallization and Methods of Fabricating Same Application Type: Utility Patent Number: 6919639 Country: United States Status: Filed on ...
URL: https://www.src.org/library/patent/p0268/
Modified: 2005-07-19 - 22KB
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1 through 30 of 332 similar documents, best matches first.   
Results by:Thunderstone Page: 1 2 3 4 5 6 7 8 9 10 next >>