Call for Research:
Interconnect and Packaging Sciences Research Program

You may submit your White Paper online or you may send the PDF or PostScript files as email attachments to: Jennifer Minor at jennifer.minor@src.org (919-941-9415).

Goal:

The Interconnect and Packaging Sciences (IPS) area at SRC solicits white papers intended to lead to full proposals in the area of advanced Back End Processes (BEP), Packaging, and BEP/Packaging interface technology. Programs in this area are intended to provide research solutions supporting the semiconductor industry in continuing to meet Moore's Law cost/performance improvement projections.

Participation:

This RFP is open to all universities, domestic and international. It is open for researchers to participate as individual investigators, small teams, and Centers. Contracts resulting from this solicitation are anticipated to be three years in duration. The SRC expects to fund the equivalent of approximately 25 researcher/student teams from this solicitation. However, the SRC reserves the right to fund all, some, or none, of the proposed work, depending on the quality of proposals received and availability of funds. The SRC also reserves the right to negotiate with any multi-investigator proposers to increase/reduce/modify the team to meet funding and/or synergy goals.

Role:

The role of this solicitation is to stimulate non-traditional thinking about issues facing the continuation of interconnect and packaging technology up to and beyond the boundaries of the ITRS. This solicitation covers all areas of BEP, Packaging, and the interface between these two areas. Items of interest in each of these areas are described more fully in the BEP, Packaging, and BEP/Packaging Interface Needs documents contained on the SRC IPS web site.

• Back End Processes Needs Statement
• Research in Support of Convergence of On-Chip and On-Package Interconnect
• Packaging Needs Statement

White papers are invited which address one or more of the following topics:

Extendability of Cu Low-K

• Simulation-based theoretical and experimental investigations to extend the minimum geometries of Cu lines by reducing the impact of surface scattering, grain boundary scattering, point defects, and impurities. Encouraged are ab-initio simulation approaches that may relate new material or integration conditions to fundamental electron transport. Related to electron transport are issues such as Joule heating and stress management in the vicinity of the Cu network.
• Fundamental understanding of the limits of electrochemical deposition techniques for fabrication of fine lines and vias.
• Fundamental understanding (simulation, theory or experiment) of the interaction between unit processes (e.g. etch, planarization, metal deposition and fill) associated with metallization and the impact of sub-surface materials property integrity with the goal of overcoming drawbacks that compromise critical properties such as k-value. Of specific interest are fundamental (theory simulation) characterizations of how etch and cleans processes can be developed to maintain or better chemical/materials structures that lower k value.
• Investigations of alternate technologies for the deposition of metal conductors, including novel CVD, ALD, plasma-assisted approaches, electroless, electroplating and beam concepts. Included here is work that looks to extend conventional metallization processes (e.g. IPVD) beyond anticipated limits.
• New ultra-low k dielectric structures using both experimental and modeling and simulation techniques to achieve higher mechanical strength while maintaining low dielectric constant. Of importance is the impact of aggressive processes such as CMP on structure integrity. Novel non-abrasive methods of planarization failure modes (thermomechanical, electrical or chemical breakdown) are of ongoing importance.
• Investigations of fundamental issues in fabrication and reliability of ultra-thin and "zero thickness" barriers. Lines of investigation linking ab-initio methods pointing to new materials or integration techniques should be linked in some manner to an experimental effort.
• Development or improvement of unit process or unit process integration theoretical or simulation models (patterning through deposition) that in a crosscut manner can support the above mentioned thrusts.
• New metrology tools for 22nm and below interconnect use.
• New methods to characterized the reliability of large interconnect systems.
• Methodologies to predict reliability of packaged low modulus low-k dielectrics.

Novel Approaches to Interconnect and the Global Interconnect Problem

• Theoretical and experimental assessment of new concepts and radical alternatives to current interconnect and chip/package interconnect systems.
• Theoretical and experimental assessment of new features of currently proposed global interconnect and chip/package interconnect systems, including but not limited to, optical interconnects, 3D interconnects, and package intermediated interconnects. (Many of the "currently proposed" areas are also topics being pursued by other funding agencies, such as ISMT, DARPA, and the Interconnect Focus Center. To be considered for funding, white papers must clearly distinguish proposed work from on-going research).

Chip/Package System Concepts

• New concepts and radical alternatives for systems approaches to total chip-package functionality are sought. These new approaches should transcend the traditional view of chips integrated into packages. They should explore the options for providing total system performance, including, for example, digital, analog, RF and optical functionality within an integrated entity.
• Innovative chip, packaging and board approaches to minimize design architecture changes while still meeting the continued advances in performance dictated by roadmap projections.
• Chip-package co-design
• Development of methodologies to help designers decide, within the bounds of cost/performance, on SoC vs. SiP/SoP approaches. Key enabling technologies to be developed for optimized system performance should be considered.

Power Delivery and Thermal Management

• Novel concepts to dramatically change the electrical and thermomechanical interfaces between the chip and the outside world using new or revolutionary design techniques, materials, and/or fabrication technologies to simultaneously achieve high-performance and very low cost chip-package systems. Due consideration to issues of implementation of these novel concepts in a manufacturing environment is desirable.

Expectations:

Awardees in this solicitation will be expected to participate in an annual research review to describe the results of their study, and to be available for special request presentations if needed. Participants will be required to provide data on student participants on a regular basis to assist SRC member companies and students in recruiting/job hunting efforts. Annual reports consisting of an electronic copy of material presented at the annual review will be required. A short final report documenting progress for the program and suggested future directions will be required. Publications resulting from this research will be reviewed for IP content before publication, and preprints will be needed for inclusion on the SRC website.

Responses are limited to five pages and may be submitted via the SRC Web site or by e-mail (see below). White papers not meeting these requirements will not be considered.

Please include the following identifying information in your white paper:

• Project title
• Investigators
• University
• Mailing address
• Telephone number and e-mail address

Please make sure to address the following in your white paper:

• Context: emphasis area (BEP, Packaging, or Interface between BEP and Packaging)
• Rationale: value in terms of semiconductor industry needs
• Objective: What do you plan to do?
• Novelty: role of this research in advancing knowledge and state-of-the-art
• Approach: strategy for addressing the problem
• Results: anticipated output of a successful effort
• Funding: a per-year approximation of overall funding needs (university approval and budget not required at this time)

Awardees will be expected to:

• Disclose blocking background intellectual property
• Update information about participating students
• Submit publications resulting from sponsored research
• Participate in annual research reviews
• Provide annual reports and pre-defined deliverables

Funding in this solicitation will be divided among programs emphasizing BEP or Packaging interests and programs addressing the interface between these two areas. All three of these areas are expected to be well represented in the final proposals selected. However, the final distribution will depend on the quality and strength of white papers and final proposals received.

You may submit your White Paper by sending the PDF or PostScript files as email attachments to: Jennifer Minor at jennifer.minor@src.org (919-941-9415).

Address technical questions to: Harold Hosack, Director of IPS, at harold.hosack@src.org (919-941-9485 or 919-941-9400).

Submission Deadline: June 28, 2004 at 5:00 PM EST.