System for Placement Optimization of Chip Design for Transient Noise Control and Related Methods Thereof

    • Application Type:
      Utility
      Patent Number:
      10417367
      Country:
      United States
      Status:
      Filed on 1-Jun-2015, Issued on 17-Sep-2019
      Organization:
      University of Virginia, Charlottesville
      SRC Filing ID:
      P1866

    Inventors

    • Ke Wang (Univ. of Virginia)
    • Kevin Skadron (Univ. of Virginia)
    • Mircea R. Stan (Univ. of Virginia)
    • Runjie Zhang (Univ. of Virginia)

    Related Patents

    P1538
    Application Expired
    STARnet

    System for Placement Optimization of Chip Design for Transient Noise Control and Related Methods Thereof

    Kevin Skadron (Univ. of Virginia); Mircea R. Stan (Univ. of Virginia); Ke Wang (Univ. of Virginia); Runjie Zhang (Univ. of Virginia)
    Patent Application Expired
    Application Type: Provisional
    P1867
    Issued
    STARnet

    System for Placement Optimization of Chip Design for Transient Noise Control and Related Methods Thereof

    Kevin Skadron (Univ. of Virginia); Mircea R. Stan (Univ. of Virginia); Ke Wang (Univ. of Virginia); Runjie Zhang (Univ. of Virginia)
    Patent Issued (on 6-Sep-2022)
    Application Type: Divisional

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