System for Placement Optimization of Chip Design for Transient Noise Control and Related Methods Thereof

    • Application Type:
      Divisional
      Patent Number:
      11436401
      Country:
      United States
      Status:
      Filed on 16-Sep-2019, Issued on 6-Sep-2022
      Organization:
      University of Virginia, Charlottesville
      SRC Filing ID:
      P1867

    Inventors

    • Ke Wang (Univ. of Virginia)
    • Kevin Skadron (Univ. of Virginia)
    • Mircea R. Stan (Univ. of Virginia)
    • Runjie Zhang (Univ. of Virginia)

    Related Patents

    P1538
    Application Expired
    STARnet

    System for Placement Optimization of Chip Design for Transient Noise Control and Related Methods Thereof

    Kevin Skadron (Univ. of Virginia); Mircea R. Stan (Univ. of Virginia); Ke Wang (Univ. of Virginia); Runjie Zhang (Univ. of Virginia)
    Patent Application Expired
    Application Type: Provisional
    P1866
    Issued
    STARnet

    System for Placement Optimization of Chip Design for Transient Noise Control and Related Methods Thereof

    Kevin Skadron (Univ. of Virginia); Mircea R. Stan (Univ. of Virginia); Ke Wang (Univ. of Virginia); Runjie Zhang (Univ. of Virginia)
    Patent Issued (on 17-Sep-2019)
    Application Type: Utility

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