2005 GRC Compelling Research Reasons

Research details: In flip-chip assemblies, delamination often initiates at stress singularities associated with corners and edges. It this study, the stress state associated with such singularities will be accurately modeled using a specialized finite element program-FRAC3D. It is anticipated that these calculations, in conjunction with measurements obtained from Prof. Pearson#s parallel task: Crack Initiation Studies at Interfaces Relevant to Flip-Chip Assemblies, will permit prediction of crack initiation in Flip-Chip packages

Impact statement: AMD has used the fracture mechanics tool (frac3D) for the last 2 years to give us superior results in predicting chip/package mechanical interactions.

Research details: Investigating the Effects of Added Base on Photoresist Line Edge Roughness

Impact statement: Understanding and finding ways to reduce the LER which is already having an effect upon leading edge lithography, contributes to improved distributions of device performance.

Research details: The proposed project will investigate the structural/chemical stability of the barrier layer and its impact on physical reliability of low-k/Cu interconnect structures, with variation in material type, dimension, ambient, degree of porosity, and processing condition. In particular, critical factors affecting the reliability of the barrier integrity will be identified.

Impact statement: At Techcon 2000 Craig Barrett forecast a major reliability crisis sometime soon, merely because we hadn't had one recently! Work such as this has prevented our industry from having a major rel. crisis in recent years, and should continue to prevent one. A SUBSTANTIAL SAVINGS TO THE INDUSTRY!

Research details: Methodologies and corresponding software for generating effective N-detect test sets, and experimental data showing the effectiveness of the developed methodologies.

Impact statement: Companies drive research into problem areas causing test escapes, the Universities make progress in solving them, and the ATPG vendors improve the tools which benefits the companies. Real Value in these colaborations.

Research details: Prof Engelstad's work on mix-and match overlay using EUV for certain layers revealed the need to adopt a systematic mask clamping system for the reticle during its lifetime.

Impact statement: Estabishes a knowledge base from which we can develop the necessary manufacturing procedures to ensure success in applying EUV lithography.

Research details: 1. Modeling Worst-Case Inductive/Capacitive Effects - Given an interconnect bus, we must be able to describe the set of signal transitions on the bus lines which create the worst-case delay problem on a bus line. This problem has been explored for capacitive effects alone but this research will expand previous analysis to include inductive effects as well. The results will be applicable to noise-related interconnect testing in general and will not be restricted to the phase coding techniques which they are investigating.

Impact statement: Very interested in whether we are modelling interconnects properly. This work should impact the timing analysis tools and methodologies, leading to higher frequencies of product performance.

Research details: New circuits to efficiently characterize high-speed differential I/O signals. An example high-speed I/O BIST system on an NSC product prototype. On-chip test techniques to measure RMS, output deterministic and cycle-to-cycle jitter for 1 to 10 Gb/s I/O using minimal tester time (small number of averages).

Impact statement: Prof Eisenstat's ideas should lead to a much lower cost test platform for microprocessors which would save AMD significant funds. In addition specifications should improve, which will benefit our customers.

Research details: Adaptively-Controlled Execution for Power and Performance Professor Margaret Martonosi

Impact statement: Some of the techniques being investigated in Professor Martonosi's research, specifically, the use of performance monitors in conjunction with linear PID controllers shows tremendous promise as possible methods for optimally managing the power and performance levels of microprocessors as their workloads vary over time.

Research details: A. Galvanauskas, J. Nees and G. Mourou; Univ. of Michigan. This ambitious work on EUV power sources has started to yield good results this year.

Impact statement: Hopefully this work will lead to a cost effective solution of the need for 180W EUV power. This solution would provide several million $$ per year in operating cost savings.

Research details: Chris Ober's group at Cornell is doing uniquie resist formulation work related to EUV. Their materials are currently being tested at the Berkeley micro-exposure station.

Impact statement: Influence upon the resist suppliers in formulating effective EUV resists will be of great value. We need new thinking in this area is vital.

Research details: Chip-scale Cooling with On-chip MicrofluidicHeat Sink and Integrated Thermal-fluidic I/O Interconnects

Impact statement: Control of thermal gradients at high power densities limits our ability to set safe operating limits, constraining the product roadmap. Success in research such as this has the potential for a significantly new product roadmap.

Research details: Our objective is to design a very low-power, adaptive receive equalizer for applications above 10 Gbps by leveraging our experience in on-chip LC passive component modeling and RF circuit design.

Impact statement: Significant power reduction compared to today's methods.

Research details: This project will develop models and simulation tools to predict chip failure rates due to breakdown of low- k dielectrics in backend process flows. Methodologies will be established for area scaling and to account for the wide variety of electric field distributions within low-k insulators between chip interconnect lines.

Impact statement: Current technologies for reliability estimation are becoming inadequate. We have high hopes for Professor Milor's new work.

Research details: Tim Cheng - Santa Barbara ATPG based model checkers

Impact statement: Tim Cheng maintains arguably the top open ATPG engine, this has proved very useful to Cadence for benchmarking

Research details: Multiple projects from the following PIs: Allstot -Washington State Wolley - Stanford Moon - Oregon State Fiez - Oregon State

Impact statement: Data converters for consumer and communication applications are a specialty of Cadence Design Services. Low voltage, low power techniques developed by these researchers have been used in design for Cadence customers

Research details: Multiple PIs in area of Frequency generation Ismail - Ohio State Mayaram - Oregon State Harjani - Minnesota

Impact statement: To Cadence Design Services, highest speed and highest accuracy are critical in oscillators and PLLs. Very clean clocks are a Cadence specialty

Research details: Somenzi/Hachtel

Impact statement: They develop/maintain CUDD & VIS, standard packages used by many in the industry. They keep these packages current with cutting-edge technology, providing a valuble service

Research details: Ringo, Wash State

Impact statement: Introducing new circuit techniques extends the use of analog EDA tools, of great importance to Cadence's analog suite of tools. Cadence's Design Services does contract design on Analog, Misec Signal & RF and the preparation of design kits to Accompany these tools. Three areas of CDADIC research are particularly important: Data Converters ' DACs & ADCs, Frequency Generators — Oscillators & PLLs, and ESD and Reliability structures

Research details: Randy Bryant's work on UCLID

Impact statement: The work on UCLID is very fundamental and has many applications in hardware and software verification. The chosen abstraction provides a practica compromise between expressivness and efficiency.

Research details: Ed. Clarke's work on SystemC verification

Impact statement: The work on software and SystemC verification performed by that group is ground-breaking and leading edge. It finally moves us from traditional RTL-style verification into the system space.

Research details: Rosenbaum - UIUC

Impact statement: Cadence provides design services to customers in the most difficult design areas. ESD protection of the highest speed circuits has not been properly addressed by industry. Her research is particularly useful in getting the high speed of the porcess realized in the chip's I/Os

Impact statement: They have provided a HF full-wave electromagnetic momentum structure simulator, UA-FLIS, that is 10X faster than other simulators. They're currently adding other features that should make this simulator more accurate and we intend to use it when they finish. The new sparse matrix method should especially help with large structures.

Impact statement: Ge is a strong contender for next generation CMOS. Based on their earlier work on III-V surfaces, the Kummel group has a strong and unique expertise in oxide/semiconductor interface preparation and analysis. (1) The Kummel group has developed a technique of depositing monolayers of SiO (silicon monoxide) in an oxygen-free environment thereby preventing formation of GeOx (germanium oxide); GeOx is known to pin the Fermi level. The SiO leaves the Fermi level unpinned and other groups have shown that the high-k HfO2/SiO interface is unpinned. (2) The Kummel group has developed a method of reliably preparing unpinned Ge(100) in UHV. This is critical to any Ge MOSFET.

Impact statement: Dr. Gard's efforts on this project are appreciated. They have successfully taped out their first design for phase I of this project which includes a folded input stage upconverter/modulator, quadrature generation and PA pre-driver amplifier. This research has been and continues to be of benefit to Freescale in defining our next generation 3G architecture.

Impact statement: The CAIST projects are developing fundamental understanding of the ultimate limitations of different types of interconnect which is vital in setting future directions. This basic work helps illuminate which technology directions are more likely to be beneficial in solving the interconnect bandwidth and latency issues. The optical interconnect project is beneficial in two fronts: 1) The basic system level analysis will serve as a guideline for when optical interconnect systems will be required and the tradeoffs associated with various implementations. 2) The expermental work will be focused on the development and optimization of components (Si-compatible sources and amplifiers) that would be fundamental in the construct of OI.

Impact statement: Low power is becoming a key diffrentiator for competing in the market place for all segments of FSL operations ( wireless, networking, communication, computation, etc.) Analyzing the impact of high level microarchitectural decisions on performance as well as power is of prime importance. The research project headed by Professors Dutt and Kurdahi at UC-Irvine is tackling this problem and we are collaborating with them to apply their techniques to our designs. Some of the early results on analyzing the impact of thermal variations on leakage power are quite novel.

Research details: Warp processing defines a broad research framework that can be utilized in a wide variety of applications.

Impact statement: Warp processing defines a broad research framework that can be utilized in a wide variety of applications. Excellent research in the area of binary acceleration using real time profiling and design tools. Identifying coding styles that lend themselves to effective optimization.

Research details: Provide an improved fundamental understanding of metal gate interaction with high k gate dielectrics including the development of work function extraction methodologies. To achieve band edge work function, novel metal alloys will be explored.

Impact statement: Data generated in this task for novel metal gate stacks on HfO2 and Hf-silicates can assist learning for metal-gate materials not available at FSL.

Impact statement: Revolutionary approach to further generation resist chemistry. The approach is this project could solve LER issues which will have a significant impact on present and further resists.

Impact statement: The work at UWM covers near and long term areas of study. The most immediate impact has been from R. Engelstads's mechanical modeling work which has provided key information to tool and photomask suppliers improving designs for reticle and wafer chucking, and fluid dynamics in immersion lithography.

Impact statement: The research has provided much needed data and fundamental studies on the EM induced failures in leaded and lead-free solders in ceramic and plastic packages. Theoretical understanding of the EM induced intermetallic formation and their effects on the bump characteristics was obtained, which is critical for the next generation of packages.

Research details: (1068.003 Edwards) Quality compiler provides option to commercial tools.

Impact statement: (1068.003 Edwards) Esterel compiler technology can be very valuable as a verification test suite creation tool.

Research details: Professor Roy consistently produces interesting results that are well supported by theory and a path to implementation.

Impact statement: Aggressive exploration of low power in nanoscale technologies. Professor Roy consistently produces interesting results that are well supported by theory and a path to implementation.

Impact statement: With the shrink of the process, the random/system process variation has become the major concern of circuit design and optimization. This project has provided various solutions for optimization in this uncertainty situation. The recent work includes statistical full-chip leakage analysis and transistor sizing with statistical modeling. This work can effectively improve our design quality or yield.

Research details: Sanjay Banerjee, UT Austin, Ge CMOS

Impact statement: The PI has achieved selective epitaxy of Ge on Si for CMOS applications. Ge on Si PMOS shows 2X drive current enhancement compared to Si control, an important result. Properties of HfO2 on Ge are determined using transistors and MOSCAPs. Work is ongoing to determine how much carbon is in Ge:C alloys grown on Si by CVD.

Research details: Device simulator to predict short channel MOSFET performance for'position-dependent, general stress' tensor. Summer 2005 intern implemented PMOS <110> stress model and work is continuing through 2006.

Impact statement: Will greatly benefit CMOS process development by providing an understanding of the most effective and scalable stressor combinations. Enabled through a device simulator to predict short channel MOSFET performance for position-dependent, general stress tensor. A PMOS <110> stress model was implemented through a summer intern and work is continuing through 2006.

Research details: Power and Area Efficient Network-on-Chip Architectures

Impact statement: Novel intra-chip communication. Gaining knowledge in NOC architecture including the development of new algorithms, protocols and techniques for NOC routing, congestion control, deadlock avoidance and topology design. This research has very high potential to accelerate several R&D projects involving design of on-chip multi-core interconnection.

Impact statement: A methodology has been developed for placement and sizing of on-chip decoupling capacitors. The methodology has been tested through simulations, showing reduction of power-grid noise of at least 200% as compared to existing methods of placing on-chip decoupling capacitors. The methodology is fundamental in future technologies to improve the Ldi/dt noise on power-ground lines in mixed-signal high frequency (high slew-rate) applications. One more student (for a total of two) has been allocated by the PI to the project, a good aspect.

Research details: Project 1232.001: Evaluation of Wafer Bonding Impact on Strain in Active Silicon in Monolithic Wafer Level 3D Stacks

Impact statement: The RPI group has provided valuable wafer bonding and thinning research that enabled the bonding of several types of SOI wafers with and without TEOS deposited. The impact of the first phase of the project is to demonstrate a change of SOI Si stress after bonding and thinning a single SOI wafer. The second phase will measure the cumulative change in stress after successive wafers are bonded and thinned. This research is making significant progress in the understanding the impact of 3D integration on functional wafers.

Impact statement: The research team at USC headed by Prof. Breuer and Prof. Gupta has been working on developing sophisticated tools and methodologies for targeting performance failures. Thes kind of failures are becoming very important for 90nm designs and below, especially high performance designs. Understanding the root cause of those failures and building automated tools for diagnosing those failures is key to be able to improve the design margins and increase yield. This is the underlying research that can lead to optimized DFM rules, higher yields, and lower IC cost.

Impact statement: The task involves development of a one of a kind plasma reactor modeling code. The reactor model is used in freescale to model plasma processing tools, most recently ICP tools used in gate etch. Has enabled modeling studies of issues such as profile control and line end pull back at gate etch, finfet manufacture, and metal gate etch.

Research details: This project is developing a mesoscale model of resist chemistry under custom funding from several companies

Impact statement: This project is developing a mesoscale model of resist chemistry that could prove to be very valuable to understanding the causes of line edge roughness. Line edge roughness will have increasing impact on the performance of transistors and critical timing paths.

Research details: Rutenbar is progressing towards a realizable, cost effective architecture. A true mobile, low power solution needs to be the ultimate goal.

Impact statement: Optimizing speech recognition in embedded systems could open many interesting applications. Rutenbar is progressing towards a realizable, cost effective architecture. A true mobile, low power solution needs to be the ultimate goal.

Research details: This project explores a few novel approaches to form strained Si channel MOSFETs using recessed SiGe source/drain junctions for future CMOS technology nodes.

Impact statement: This project explores a few novel approaches to form strained Si channel MOSFETs using recessed SiGe source/drain junctions for future CMOS technology nodes and will help us understand the potential application of the recessed SiGe junctions in 45nm CMOS technology and beyond.

Impact statement: The researchers have started to make very interesting progress toward the method and tool for systematic analog and mixed signal transceiver design. The research, when completed, will enable the system designer to get closer to optimum transceiver implementation which is important for most system designs.

Research details: In the first phase of the project the authors are expected to measure thermal and electrical conductivity of different barrier materials, Ta, TaN and bilayer.

Impact statement: 1292.012 Joshi & King. In the first phase of the project the authors are expected to measure thermal and electrical conductivity of different barrier materials, Ta, TaN and bilayer. The data will be needed for the simulation of Joule heating effects in the backend of the current (65 nm) and future (32 & beyond) technology nodes.

Impact statement: This research by PI Bruce Wooley is focused on low-voltage (< 1.2V) high-dynamic range (12 bits) wide-bandwidth (10MHz) oversampled digital-to-analog converters (DAC) in deep-submicron CMOS processes. Peformance at the targeted levels would enable higher levels of integration and improved performance in a number of wide-band communications applications. The research was just funded in May 2005 and will be complete in April 2008.

Impact statement: This research by PI Un-Ku Moon is focused on taking advantage of universally available low-cost digital CMOS transistors to calibrate out the problems with analog circuitry that arise when designing precision analog-to-digital converters (ADC) in deep-submicron CMOS. Peformance at the targeted levels (10-15 bits at 20-200MHz in sub 1V CMOS) would enable higher levels of integration and improved performance in a number of wide-band communications applications. The research was just funded in May 2005. Because of its focus on ADCs, this research is a worthwhile complement to the research described in task 1307.001.

Impact statement: The research project headed by KT Cheng and team at UC-Santa Barbara is tackling the hard problem of equivalence checking at the sytem level. As higher levels of abstraction above RTL gain more acceptance within the design community, the need for methods to verify the equivalence of high level design descriptions against lower level implementations is essential. The team at UCSB has been at the forefront of this hard research problem and they have developed several hybrid engines to tackle complex designs.

Impact statement: Developing new DFM tools and methodologies has been identified as a key thrust to cope with the difficulties imposed by 90nm and below. One of the key aspects of DFM is to make the design flow aware of lithography effects. The research work headed by David pan at UT-Austin is addressing this problem. There is a need for efficient techniques and algorithms to be able to manage the complexity of modeling lithography effects during the design flow without sacrificing the performance of routing, extraction, timing, etc.

Research details: Research ID: 1197 -- Improving Outlier Screening Using Statistical Post-Processing University: Portland State University PI: Daasch, Portland State

Impact statement: This research project has impact on IBM's own R&D work in the area. This is a strategically important area for IBM.

Research details: Simulator-Independent Models of ESD-Protection Devices - Elyse Rosenbaum, University of Illinois

Impact statement: This work was critical in jump starting ESD modeling in IBM. The previous student working on this project at University of Illinois was hired by IBM and contributed to this effort within IBM. The models are currently being used in IBM bulk and SOI technology. The Verilog-A language that is being used enables simulator independent usage and evaluation of the models, and further helps technology transfer.

Research details: Research ID: 1172 -- IC Deformation Characterization for Test and Yield Learning Research ID: 1246 -- Improving the Effectiveness Multiple-Detect Test Sites University: Carnegie Mellon University PIs: Maly, CMU; Blanton, CMU

Impact statement: IBM finds these two research projects to be potentially of high impact, and intends to collaborate with the PIs to evaluate them.

Research details: Low voltage PLL design tolerant to noise and process variations - Prof. Un-ku Moon and Prof. Karti Mayaram, Oregon State University

Impact statement: This work will be useful for development of low voltage design techniques that can be used for the design of noise tolerant PLLs and frequency synthesizers. Self-calibration method will be also useful to tune out PVT variations yielding a robust design. Within IBM, the results of this work can be used for low-voltage PLLs, programmable delay lines, and low-jitter ring oscillators which require high power supply noise rejection for future design.

Research details: ACI Circuit Techniques - Paul D. Franzon, North Carolina State University

Impact statement: The NC State Capacitively Coupled I/O project team has demonstrated the concept of very high density I/O at 6 Gb/s in multiple channels. They have also demonstrated that it can be scaled beyond 20 Gb/s without increasing the complexity of the circuits, which appears to be unique. In response to discussions with IBM serial link designers, the university team has demonstrated robustness to noise. The potential impact of this work is improved power, density and speed, thereby reducing the total die area used for I/O circuits.

Research details: 1188.001: Energy Efficient, Reliable On-Chip Communication Architectures 1188.002: Software Application Mapping and Simulation-Based System Design Space Exploration Tools PIs: Mary Jane Irwin, Mahmut Kandemir, Vijaykrishnan Narayanan

Impact statement: The potential impact of this work is power and reliability estimation at system level, and a multi-processor SoC simulation environment in an industry standard language (SystemC) to support architecture definition and enable system optimization. These are both very relevant to future IBM systems to evaluate different on-chip communication architectures, and to permit exploration of different configurations in multi-processor systems.

Research details: Resonant Global Clock Distributions for Microprocessors - Ken Shepard, Columbia University

Impact statement: The research on resonant clocking research done by this group is being leveraged by IBM research and development groups. One student has been hired into IBM Research to continue on research into clock distribution architectures.

Research details: Table Assisted Implementations of Integer and Floating Point ALU's for Low Power SIMD Scientific and Multi-Media Processors - David Matula, Southern Methodist University

Impact statement: The research is investigating a new multiplier design for low power, using table look-up design. This could have significant impact if it works and change the way we design floating-point units. His other two related topics are also interesting: reducing the delay of rounding in division and exploring exponential functions.

Research details: Feasibility of Implementing CMOS RF Front-End Circuits for 76-77 GHz Radar Applications - Kenneth K. O, U of Florida

Impact statement: IBM is actively developing millimeter-wave circuits in SiGe BiCMOS technologies. This SRC project is very useful in allowing us to get an early look at the capabilities of advanced CMOS for millimeter-wave.

Impact statement: Prof. Dutta has developed an impression creep technique that does quick-turn, in-situ solder creep characterization and can be used as a fast and accurate method to get large amount of constitutive data.

Impact statement: Prof. Goodson has over the years developed the ability to quantify basic heat transport along interfaces thus enabling TIM development.

Impact statement: Prof. Babu developed novel and enabling experimental techniques to study surface chemistry that resulted on a fundamental understanding of key reactions and mechanisms that are relevant to CMP.

Research details: Design and Evaluation of Power-Efficient High-Performance Processors with Programmable Fabric

Impact statement: Extracting performance from sea of transistor layouts while comprehending DFM.

Research details: Modeling Within-Die Spatial Correlation Effects for Process-Design Co-Optimization Spanos/Berkeley

Impact statement: Understanding and analyzing intra die variational effects on design

Research details: System Level Verification by High-Level Satisfiability Checking

Impact statement: Applying formal verification to system level languages and design

Research details: 460.001

Impact statement: Extensions of EUV lithography simulations to the 32nm node are used within Intel

Impact statement: Very good demonstration of the need for considering tree-like structures for reliability assessments (e.g. MTTF, stress for void nucleation). The PI has reached sound data-based conclusions that were then extrapolated to other materials/stacks: e.g. prediction that the JL product is expected to increase when using a metal cap, prediction on impact of liner thickness at base of vias.

Impact statement: Contributed to the fundamental understanding of interface delaminations and crack propagation under sub critical conditions, in the presence of different environments. The last year of this task generated results of use to PKG and BEP.

Impact statement: Prof. Tu has contributed significantly to our knowledge of electro-migration in solder systems and developed simple experimental techniques that can be readily transferred to industry. This effort is especially important given the focus on Pb-free solders.

Research details: 1082.001

Impact statement: Intel uses pieces of Willson's mesoscale models on the effects of added base on photoresist line edge roughness

Research details: Building Reliable Microarchitectures from Unreliable Devices with the Recursive NanoBox Approach

Impact statement: Architectures tolerating/leveraging unreliable devices and process variation

Research details: Outlier Screening for Reduced Burn-In Daasch / Portland State

Impact statement: Alternatives to burn-in

Research details: Power and Area Efficient Network-on-Chip Architectures Cidon / Technion

Impact statement: Novel intra chip communication

Research details: NEGF Transistor Simulation with Realistic Bandstructure Mark Lundstrom, Purdue University

Impact statement: This is a valuable research area developing models and understanding for highly scaled MOS beyond silicon. Over the past year they extended their code for arbitrary orientation, strain, heterostructures, and non-silicon materials. They were able to reproduce the effective field dependence of mobility gain for biaxial and uniaxial hole transport, validating their approach, then showed the differences in performance for different materials systems in a ballistic ultra-thin body MOS.

Research details: Epitaxial Growth of Semiconductor/High-K Ternary Oxide Heterostructures Darrell Schlom, Penn State

Impact statement: This research program is pursuing approaches for even higher-k dielectrics without interfacial oxide layers to meet ETOX scaling needs. Although not yet successful, they have used a thorough and systematic experimental approach coupled with careful characterization to understand the materials systems and work towards a feasible solution. Industrial interactions with us have been strong.

Research details: Materials Low Dimension GaN Field Effect Transistors University: North Carolina State University PIs: Barlage, NC State; Johnson, NC State

Impact statement: This high risk research is addressing the key issue of CMOS device scaling past 22 nm node as Si channel can no longer deliver the required mobility performance. This study of novel GaN materials system will open up a new research frontier to explore various critical issues of integration of IIIV semiconductors to CMOS.

Impact statement: Lack of understanding of dielectric performance for high speed signaling is a key gap and expected to be important to resolve as we increase signaling speeds and bandwidth. Prof. Diaz brings his considerable experience in microwave theory to help address this gap.

Impact statement: Pb-free solders are important for the electronics industry going forward. The first generation choice of SnAg solders has been arrived at based on currently available solders however there are reliability concerns due to the high melting points and relatively poor compliance characteristics of SnAg solders. There is a strong need to focus academic research attention on developing the next generation of solders that address SnAg concerns, The RE strengthened solders offer such an opportunity and Prof. Chawla, based on his background is the right researcher to conduct this research.

Research details: 1292.010 Reliability of Porous Ultra Low-k Dielectrics: Fracture and the Effects of Environment; Joost Vlassak and Roy Gordon; Harvard University

Impact statement: High potential approach for correlating mechanical measurements (4-point bending, nanoindentation, membrane technique) to physical measurements (FTIR, RBS), which reveals the underlying relevant mechanisms that define the mechanical behavior of porous low k materials. Work on ALD deposition of barriers, adhesion and seed layers is also promising.

Research details: 1292.004 Electron Scattering at Cu-Interconnect Surfaces Daniel Gall, RPI; Hong Guo, McGill University

Impact statement: This task tackles a central issue of the BE from both experimental and first-principles perspectives. This task can potentially provide a fundamental understanding of the role of specularity on resistivity, which could lead to novel solutions.

Research details: 1292.017 Interfacial Chemistry and Atomic-Scale Reactions in Ultra-Thin and Zero-Thickness Barrier Layers for Copper Interconnect D. Muller / Cornell

Impact statement: Prof. Muller and team adapted known techniques (EELS and STEM) to analyze film properties and interfaces. The analytical toolset that has been devised by the PI is cutting edge and easily transferable to Industry. This past year, the group gathered EELS fingerprints for identifying reactions at interfaces between Cu and liner materials with subnanometer resolution.

Research details: PI: Prof. E. Madenci, Univ. of Arizona, Tucson Customized LSI Research: TESTING AND SIMULATION TO QUANTIFY THE INFLUENCE OF MOISTURE AND TEMPERATURE ON IC PACKAGE RELIABILITY

Impact statement: It is difficult for us to determine the correct baking times of packages to eliminate entrapped moisture. The program that we started with University of Arizona, Tucson is providing us the characteristics of currently used material properties in flipchip packages which are not available from the vendors. In addition, a model is in development to predict the baking time. With the correct baking time, we would be eliminate the entrapped moisture in the packages; therefore the moisture related failures during reflow of the package to the customer's board would be eliminated.

Research details: Interconnect Design for Integrated Synthesis/Layout System The project is custom funded by IBM PI: Jiang Hu, Texas A&M University

Impact statement: As interconnect delay becomes the predominent part of the overall delay, more innovative techniques (methodology, tools) are required for optimized the performance and power in SOC. The impact is very significant, since performance and power severely impact the part cost. Designing an interconnect system for design optimization is not only a matter of optimizing the interconnect architecture/geometry, but also to consider the environment. Repeater architecture is for instance part of the interconnect architecture optimization.

Research details: PI: Borijove Nikolic, Univ. of California/Berkley Reseach is a custom project funded by Cadence.

Impact statement: The Power-Performance Trade-off in ASICs is very important for future technologies. The goal is to be able to meet the performance requirements and still use cheap packages. Impact: The cost savings for high volume ASIC can be very significant.

Research details: Low Cost Testing of High-Speed DACs and ADCs. RF Load Board Design and Analysis of Test Measurements.

Impact statement: High speed SERDES technologies are being worked on at LSI and are part of our standard IP offering. There are several challenges being faced by the industry in creating load boards for SERDES. Increasing cost for testing analog functions needs to be controlled. Research effort as part of this task will certainly have an future impact in addressing these challenges.

Research details: IC Deformation Characterization for Test and Yield Learning

Impact statement: This research addresses an emerging and growing need in the industry to be able to learn about defects from test data. This research is leading the way in a test area that currently does not have enough research behind it. Approaches such as those being investigated in this research will be vital in coming technologies to maintain yield and quality levels.

Research details: Statistical Timing Simulation Tools and Methodologies for Delay Test and Performance Validation

Impact statement: The work will be useful for designs in 65nm or later technologies. Comprehending induced affects because of cross talk, power, noise and process variations will be key in maintaining the effectiveness of delay fault testing in new DSM technologies. For large designs, back annotated simulations may not be practical anymore and statistical timing simulation tools possibly can help overcome the problem.

Research details: Test Development for Mixed-Signal, Hierarchical, and Heterogeneous SOCs

Impact statement: Analog test frequencies are increasing rapidly and the solutions coming from the research work will enable us to meet some of the challenges. Addressing silicon overhead for analog test wrappers and cost reduction by allowing the use of analog test wrappers at wafer sort will be directly beneficial to us.

Research details: Diagnosis for Performance Failures Considering Realistic Noise, Process Variations and Defects

Impact statement: Targeting design integrity induced effects in conjunction with defects is key to addressing test escapes and reliability problems at 90nm and below. LSI would like to see EDA companies be mentors to this work, so as to guide the PIs into algorithms that will be amenable to productization in their toolset, which will eventually benefit tool users like us.

Research details: Test Generation, Avoidance of Overtesting and Test Data Compression for DSM designs

Impact statement: Efficient and cost effective test is key to reducing both the 1-time test pattern generation cost, which is quite high for delay fault patterns as wells as the recurring test application cost. Yield loss minimization is key as well and this research focuses on these 2 aspects, which are considered key by LSI.

Research details: Improving the Effectiveness of Multiple-Detect Test Sites

Impact statement: Given that we have a good understanding of the impact of probabilistic N-Detect scheme and the fact that our EDA partner is pursuing BCE+ and Determistic Bridge pattern generation approaches, the tool developer can gain additional insights into their bridge candidate filtering based on this research which will eventually benefit tool users like LSI.

Research details: Functional Silicon Devices with Atomically Precise Doping; M. Y. Simmons/UNSW, A. R. Hamilton/UNSW, L. C. L. Hollenberg/Melbourne, and L. Oberbeck/UNSW; Univ. of New South Wales; 19-Sep-2005; pp.; (Pub P013411); Task 1276.001

Impact statement: With the scaling down of technology to 65nm node and lower the device channel length shrinks to less than 45nm. At these small geometries, dopant profiles, their number and position within the device play a critical role in achieving transistors with reasonable and reliable characteristics. The approach used by Prof. Simmons and her team allows for such a precise control of dopants within the device. In addition, their approach allows for forward looking investigations into the scaling limits of CMOS technology as well as possibility of creating new improved devices/switches by controling the placement of atoms next to each other.

Impact statement: Helped us recognize Chew's seminal contributions to Field Solver solutions, that were somehow hidden from the view in our community

Research details: The authors expanded from the quasi static solvers successfully introduced a decade ago ( FastCAP & FastHenry), well into a high frequency domain , with wavelengths comparable to the feature dimensions complex scale in EM. Their current research in volumetric approach in conjunction with fast solvers, is the natural candidate to become the future gold reference in Industry.

Impact statement: Provides focus in our ongoing activities in this endeavor. Has the potential of becoming the golden reference in the industry for high frequency parasitic effects.

Impact statement: The PI follows a parallel track to our needs, providing good reference information.

Impact statement: The work that Jim Meindl and his students perfroms is invaluable to us in that it provides a constant calibration for our future needs and directions, by looking at alternatives and fundamental limits, from much more of a design point of view that we could handle internally.

Research details: as a continuation of 1293.001

Impact statement: Mark Kushners plasma modeling. HPEM to be precise, has positively impacted four of our Business Units; PECVD, PVD, HDP and SIG. This is an outsanding resource which provides world class technology which continues to help us, and our customers.

Impact statement: Scaling of Copper Resistivity beyond 45nm is one of the most important issues we need to understand. TS Kuans work is helping us in this arena greatly. The work is ongoing but the greatest impact is still in the future.

Impact statement: Fundamental studies of plasma-surface interactions is obviously of great significance to a plasma oreinted company. The work on the effects of radicals and ions potentisally can have considerable impact on both our low k programs and ALD programs.

Impact statement: Electromigration Reliability for Solder Balls in Plastic Flip-Chip Packages.

Impact statement: This research is delivering fundamental new modeling techniques for analyzing crack initiation and propagation behavior in solids. One strength of the technique is its ability to allow re-calculation of the stresses resulting from a crack propagating without require re-meshing of the solid model. This enables a vast array of problems to be addressed which were too difficult before. It also couples fundamental lattice constants and quantum physics of materials to the calculation, allowing it to bridge the gap between full molecular level and continuum analysis. We envision this type of tool being used to analyze problems as diverse as stress driven lattice defects, crack propagation in porous low-k dielectrics, interfacial delamination, polymer fatigue at interfaces, and crack scattering from filler particles.

Impact statement: This research will allow the generation of compact models incorporating NBTI degradation that will allow TI designers to accurately incorporate these effects in their circuit designs.

Impact statement: Scaling of Cu Resistivity Beyond the 45nm Node: Effects of Ultra-Thin Liner Materials on Surface Scattering and Cu Grain Growth Quantitative understanding of the electrical resistivity of Cu and Cu alloys as dimensions shrink well below 100nm. Also impact of Cu/liner interactions and anneals.

Impact statement: Chip-Package Interaction and Reliability Impact for Cu/Low k Interconnects.

Impact statement: Modeling and controlling the pattern dependency of selective epitaxial SiGe deposition is critical for this technology to be applied across a broad range of device designs at the 45 nm and 32 nm nodes.

Impact statement: Direct calculation of stress in nanoscale transistors may be enabled by measuring the density of state change.

Impact statement: Great value in EM and stress reliability investigations of Cu/low k interconnects, and methods to improve interconnect reliability at the 45nm node and beyond. Fundamental and statistical examinations of Cu/ULK reliability and failure mechanisms.

Impact statement: The work in new materials is critical to understanding the ESH issues and technical issues for new processes and technologies, particularly in the front-end area. Continuing efforts on factory integration, specifically water use reduction, continue to be important and valuable for TI in driving sustainable growth.

Impact statement: Environmentally Benign Photolithography, Deposition and Etch Processes in Semiconductor Manufacturing

Impact statement: This work provides important information on supercritical CO2 and various co-solvents, particularly in the area of low-k dielectric films. The fundamentals of this work also support the application of supercritical CO2 as a benign material for other potential applications.

Impact statement: This program provides TI with a number of unique electrical modeling tools for IC package analysis and simulation. It is in the last year of the contract but we expect it to be fully renewed shortly. In fact we are working with the PI on a new technique developed at UI to create reduced simulation files allowing much smaller SPICE representations for more efficient modeling with equivalent accuracy.

Impact statement: There have been a lot of progress made on this project. Prof. Oehrlein's group has submitted >10 conference presentations and technical papers on porous low-k etching. The group has expanded the project to study porous low-k film damage during etching and ashing (which is very important for our C014 program). They are also working with SEMATECH on low-k ash project. Their work on etch/ash chemistry selection and understanding the mechanism of ULK damage are helping us in developing our C014 etch/ash processes, and will benefit TI's C010 node.

Impact statement: Continued, good effort to measure copper resistivity, and to provide new insights into the factors that affect copper resistivity in progressively narrower lines (representative of the 32nm node).

Impact statement: Good use of statistical EM structures and Monte Carlo simulations to identify early versus late EM failures and to understand the mechanisms that lead to these failures.

Impact statement: Insightful work that correlates ALD precursor chemical composition/structure to film properties. Innovative work on synthesis and screening of new precursors for barrier applications.

Impact statement: Quantitative understanding of the electrical resistivity of Cu and Cu alloys as dimensions shrink well below 100nm. Also impact of Cu/liner interactions and anneals.

Impact statement: Great value in EM and stress reliability investigations of Cu/low k interconnects, and methods to improve interconnect reliability at the 45nm node and beyond.

Impact statement: Examining the role of additives on electrochemical nucleation and growth of copper on patterned and non-patterned barrier materials has been critical for our interconnect efforts.

Impact statement: Addresses a critical issue, barrier oxidation, that will need to be resolved for successful implementation of directly platable barriers. Such barriers may be necessary for Cu resisitivity reduction beyond the 32nm node.

Impact statement: Excellent and timely extension of evaluation of single metal silicides to metal-alloy silicides for non-dopant-based work function tuning, again positioning her group at the forefront of this field well ahead of most other groups.

Impact statement: Understanding the microscopic bonding and chemistry at interfaces between Cu and different liner materials, and correlate this information with adhesion and EM performance.

Impact statement: The on-going research into high-k dielectric etching chemistry, and post-etch clean, is of value to TI for it's own integration of high-K dielectrics at the C014 node and beyond. New developments this year include: 1) Ar dilution of H2 cleaning plasmas to reduce silicon loss; 2) demonstrated superior Si selectivity of H2/Ar chemistry over I2/Ar chemistry for residual B removal; 3) alternative non-boron-containing high-K etch chemistries, including CHF3.

Impact statement: This work has produced fundamental understanding and subsequently models used in our development at TI. For example, the past work on fluorine produced a deep understanding on the behavior of fluorine in silicon and was quickly incorporated in our simulators. One of the problems with understanding materials behavior under strain is the lack of experimental techniques. Theoretical atomistic methods allow us to circumvent this inherent disability. They have developed a fundamental framework (using DFT calculations) to look at behavior of dopants and defects for strained silicon and SiGe. They plan to extend their methodology to look at extended defects (like dislocations) as well high Ge concentrations in their future work. This would allow us to better understand and leverage the ultimate limit of strain in silicon devices (since dislocations would limit the amount of strain rather than our ability to add more strain).

Impact statement: Studies to determine whether group IV impurities might be useful in enhancing dopant solubility. Combinations with compensating induced strains (B/Ge, B/Sn, B/Pb, and As/C) were selected as most likely to give significant binding.

Impact statement: This research continues the study of the recessed strained silicon germanium source/drain junctions (developed in the FEP Research Center, 616.009, Ozturk) and the resulting strain in the channel. Implications of this research will be significant through at least the 32 nm node.

Impact statement: This work investigates the structural/chemical stability of the ultra-thin Cu barriers and their impact on the physical reliability of low-k/Cu interconnect structures, and includes the development of novel, rapid characterization techniques for barrier integrity in actual Cu/ULK damascene structures.

Impact statement: Mixed-signal production load board complexity is increasing rapidly. This means our future mixed-signal load boards will have up to a thousand relays and hundreds of passive components on them. A failure in any of these components can lead to significant production down times. Quickly diagnosing the root cause of failure is the key to ensuring smooth production run. Prof. Kim's research at University of Alabama is developing a CAD tool that will automatically generate the load board diagnostic program from given the load board schematic and information about the tester configuration. This tool will help business units to save up to a man month of engineering time per load board design. Further the tool will ensure fast and automated test hardware diagnostics capability during production testing. We are planning to fan this tool out to TI product engineering community. A student who has been working on this project accepted a job offer from TI.

Impact statement: Provides a very comprehensive and useful database of galvanic corrosion potentials for Cu and potential barrier materials which is critical for understanding and resolving galvanic corrosion issues that might arise when new barrier materials are integrated in Cu-Low-k schemes.

Impact statement: Elimination of Bimetallic Corrosion at Dissimilar Metal Interfaces in Next Generation Cu Interconnect

Impact statement: Oliver's work covers academic aspects of plating and corrosion but is also very practical as we've been taking basic pH and chemistry tests and then following through with testing actual slurries and cleaning chemistries that we expect to be using at 45nm. Emphasis on Ru as a barrier means this work is likely more useful potentially for 32nm as Ithink 45nm is lining up to extend TaN but this kind of work does need to be done.

Impact statement: Outlier Screening for Reduced Burn-In: TI has begun implementing its own post-probe statistical outlier flow and its use on production silicon data has been very helpful when applied to a current process node yield/qual issue. These techniques have also been used in a partial burn-in flow without sacrificing reliability DPPM. Application of these ideas in both of these examples has already saved TI much more than the cost of this research. We are already applying the statistical screens co-developed with Portland State University to disposition our 65nm driver device, and we expect that this technology will be critical to helping TI achieve our reliability DPPM goals early in the overall process development cycle so that we can meet our customer commitments. The work has also allowed for quick and automated identification of potential reliability screens with less engineering interaction than previous methods. Finally, the collaboration format has worked well with production

Impact statement: Near-field scanning optical microscopy Raman may enable nm scale non-destructive strain metrology. Strain is a key device performance enabler through at least the 32 nm node; strain metrology has not kept pace with the process and materials advances in this technology.

Impact statement: Prof. Lenahan's work is aimed at unambiguously identifying the atomic scale defects involved in NBTI. Towards this goal, he has used a very sensitive electrically-detected electron spin resonance technique called spin dependent recombination [SDR] to observe and identify defect centers generated during NBTI in fully processed SiO2 and plasma nitrided oxide (PNO) based pMOSFETs. In SiO2 devices, he has observed the NBTI-induced generation of two Si/SiO2 interface silicon dangling bond centers (Pb0 and Pb1). His recent results on PNO devices indicate NBTI-induced generation of a new defect center. These results provide fundamental understanding into NBTI degradation and recovery mechanism.

Impact statement: Advanced TEM techniques such as high resolution phase contrast imaging (HREM) and convergent beam electron diffraction (CBED) are used for measuring local changes in lattice parameter due to strain. Strain of the order of 2x10(-4) can be detected by the CBED method based on the strain induced shift of high order Laue zone (HOLZ) lines. As a result, it is possible to map process-induced and/or new device structure-induced strains in the active region of a local isolated device with nanometer spatial resolution.

Impact statement: These programs providing a galvanic corrosion potential database for Cu and a host of potential barrier materials to avoid corrosion during back-end processing. A dynamic, rapid corrosion testing methodology is being developed to evaluate copper's tendency to corrode in contact with new barriers.

Impact statement: Provides an excellent and practical means for detecting galvanic corrosion that is likely to occur with the introduction of new barrier materials in Cu-Low-K integration.

Impact statement: Oliver Chyan developed a neat optical method for watching Cu disappear when in contact with different barriers and in different solutions. This technique along with the usual battery of electrochemical methods was put into play on his new project with SRC.

Impact statement: This detailed study of Ru/WNx and Ru/WCNx interfaces is a stepping stone to understanding the role of interface stability and the use of Ru as a glue layer in copper metallization.

Impact statement: Ruthenium Deposition on WNx, and WCNx Substrates: Surface Science Studies of Ru/Substrate Interactions and Modifications for Enhanced Interfacial Stability

Impact statement: High value for ALD of composite, conducting, metal/nitride/silicon barrier materials, including studies of new precursors and surface modification of dielectrics to enable conformal growth of high-integrity barriers. The work includes chemical and material insights to enable Cu extendibility to future technology nodes.

Impact statement: This work helps supports filling of fine-line Cu line by studying opportunities to electroplate Cu directly (seedless) on Cu barriers. Also, examining the role of additives on electrochemical nucleation and growth of copper on patterned and non-patterned barrier materials has been critical for our interconnect efforts.

Impact statement: This work is providing a fundamental understanding of the differences in plasma surface interactions and surface modification mechanisms during plasma etching of ULK dielectrics, including nanoporous silica.

Impact statement: this projects explores seedless metallization and this might be necessary for ultra thin lines

Impact statement: direct deposition is of strategic interest to TI

Impact statement: This program is developing process chemistries and electrochemical methods that enable fine-feature Cu fill at the 45nm node and beyond.

Impact statement: This is on-going research and development of advance electrical modeling tools with a focus on speed and efficiency. We are testing the next generation software now from UAz and expect to have the most efficient tool (for a specific class of problems) available anywhere.

Impact statement: Fundamental work toward scaling Cu barriers for future nodes, including a molecular level understanding of passivation and sealing processes for metals and dielectrics. This work helps enable high performance, ultra fine feature interconnects beyond the 45nm node.

Impact statement: A Novel Approach to Seedless Cu Electrodeposition on Poorly Conductive Nanothin Ru/Barrier Electrodes: Surface Science Studies

Impact statement: This work targets a fundamental understanding of the mechanisms and kinetics associated with the delamination of BEOL interfaces (including impact of exposure to processing environments), and development of mitigation strategies, to ensure reliable Cu/ULK interconnects in current and future technology nodes.

Impact statement: This work provides a fundamental understanding and characterization of Cu/barrier/ULK interfaces, including methods to enable robust Cu interconnects for 45nm and beyond. Studies include the development of chemical methods to kinetically inhibit substrate oxide growth during Cu electrodeposition on barriers such as W and a detailed chemical understanding and control of Ru nucleation, growth and processing stability on W- and Ta-based barriers.

Impact statement: Quantification of the kinetics associated with dielectric/ULK etching, and the development of a profile simulator comprehending the kinetics of sidewall passivation, charging, sidewall roughening, and compositional dependence has been very important.

Impact statement: Modeling the life cycle impacts through the current formal standardized methods is not reasonable for semiconductors due to the large number of products, complexity of manufacturing methods and the short manufacturing duration of the product line. Increasing pressure from governments will eventually require data on Life Cycle to be developed. This research provides a method to generate accurate Life Cycle information in a shorter amount of time and will be usefull as regulatory requirements for this information are codified.

Impact statement: Cleaning systems using more environmentally benign materials will continue to be important to the SC industry to reduce the environmental impact of SC cleaning processes.

Impact statement: Identifying mixed-signal circuit applications where a three-dimensional IC technology will offer significant performance benefits over standard, planar technology.

Impact statement: Prof. McIntyre is studying the role of electrode/PZT interface on the electrical and reliability properties of FRAM capacitors. Their PZT surface studies have identified carbon based residues on the PZT films, and they have developed preliminary process conditions for their removal. Plans are in place to evaluate the impact of PZT surface modification and electrode material on the data retention and cycling endurance reliability.

Impact statement: Professor Celik-Butler's group has made significant effort in understanding 1/f noise in high-k dielectrics. The most significant contribution from this group is the comparison of 1/f noise characteristics of SiON and high-k dielectrics. Through this project we are learning the effect of interfacial engineering and bulk high-k process on the noise characteristics. In the future this program is expected to produce a SPICE model equation for 1/f noise that fundamentally is more applicable to (and accurate for) MOSFETs using high-k gate dielectrics. The most recent circuit designs for low power applications show that there is a real need for accurate noise models.

Impact statement: Investigation into the viability of III-V channel materials heterogeneously integrated with Si. Conclude that III-N materials are most promising to investigate. Provides a good basis for research in the new CMOS Extension Research Center.

Impact statement: This is a new Customized Research program starting in July, 2005. Much is expected from this program in the area of test chip design for package and system model validation. Plans are to develop test chip designs in single ended and differential output formats at frequencies of 2.5 Gb/s to 10 Gb/s over the life of the contract. Additional challenges are planned to provide internal data storage on the chip itself.