2006 GRC Compelling Research Reasons

Research details: Variability and susceptibility to soft errors in 45nm and below technologies are going to require new concepts for building reliable circuits and systems.

Technology Transfer: This research will generate new concepts for how to characterize and contain the less reliable aspects of technology. This will give rise to innovative circuit and system designs that work around and/or within these constraints.

Impact statement: Although this isn't in the forefront of many people's minds right now, I suspect that it will be within the next 5 years. Understanding how to do this may be one of the key enablers for keeping Moore's Law going in a gainful sort of way.

Research details: The whole U. Wisc Center (Nealey, Cerrina, Engelstad, and DePablo.

Technology Transfer: Resist fundamentals and limits: DePablo's model work on the structure of resist and materials properties is extremely valuable in order to gain insights into the behavior of these materials for the 22-nm node and beyond. Also, Nealey's work on templated self-assembly, while not on AMD's roadmap, may provide a good alternative in the future. Cerrina's x-ray experience and broad knowledge of resist models coupled with the interference lithography tool at the synchrotron beamline has and will continue to provide AMD with excellent insight EUV and LER issues related to shot noise and resist blur. Engelstad work continues to be of excellent value to problems that we are encountering on a shorter term, as well as for anticipating and solving future mechanical issues with EUV masks.

Impact statement: Extension of photon-based lithography and strategic understanding of issues facing 22-nm technology and beyond.

Research details: This work modesl the scheduling and routing decisions in the semiconductor production setting, and formulated an integrated model by taking into account the major operational components including demands, equipment, material supplies, workers, inventories, maintenance, and transporting tools. The model can handle existing disruptions as well as future predicted disruptions by varying parameters and decision space in a what-if analysis.

Technology Transfer: AMD is a leading practitioner of Advanced Scheduling methods as well as Advanced Process Control. In this context, handling of scheduling disruptions is important - more so within the scope of automation in 300mm fabs. A key element that already has an impact is the disruption due to APC. The application of modeling techniques on this problem will be an area of implementation.

Impact statement: The impact will be felt on equipment productivity as well as process control. Scheduling and APC have a mutual dependency and this project highlights this dependency.

Research details: Chip-Package Interaction reliability in Cu/low-k/flip-chip system

Technology Transfer: Transferred multi-level simulation methodology and experimental data from moire interferometry.

Impact statement: The 3D multi-level (or sub-modeling) technique from this task helped improving AMD's existing sub-modelling simulation technique.

Research details: Lehigh Univ, Prof. Herman Nied, on Multiscale fracture mechanics modeling

Technology Transfer: Frac3D ANSYS translator Enhanced Frac3D capability for multiscale fracture mechanics analysis Poroelasticity capability in Frac3D

Impact statement: Dr Nied did a stellar job to significantly extend already powerful capability of fracture mechanics tool - FRAC3D to address multi length scales fracture problems and modeling porous dielectrics or ultra low-K dielectrics. The tool has helped us to quantify all the major factors involving chip-package interaction for ultra-lowk Cu interconnects existing at 45nm node and beyond, hence provide a direction for us during early design state to optimize the BEoL parameters as well as package parameter to meet CPI reliability requirement.

Research details: Emerging multi-core architectures

Technology Transfer: This research will generate a better understanding of the issues, constraints and opportunities in larger-scale multi-core architectures. In addition, it will yield innovative new concepts that balance these issues in unique ways.

Impact statement: Multi-core architectures are an important aspect of computer architecture going forward. Moore's Law integration offers the transistors, and these sort of architectures can make good use of them (as long as the constraints are well understood).

Research details: Optimal placement of gates in custom design is critical to reducing power and meeting strict critical path requirements.

Technology Transfer: Tao Luo is working within AMD as a co-op to help integrate his placement and gate sizing optimization techniques into AMD flows and validating the algorithms on our production data.

Impact statement: Automatic optimization of placement and sizing for full-custom blocks will help reduce power and/or increase performance without requiring as much designer intervention.

Research details: Interfacial properties/adhesion, characterization and modeling of dielectric-to-dielectric and metal-to-dielectric interfaces.

Technology Transfer: Transferred improved adhesion and fatigue testing methodology and new understanding of materials interface issues.

Impact statement: Provides additional characterization technique and can be used with existing equipments/tools.

Research details: Prof. Galvanauskas, U. Mich.

Technology Transfer: Knowledge about progress on high-power EUV sources is very useful to evaluate the technology because this is the most critical issue for EUVL.

Impact statement: If successful, this approach will lead to much more efficient and cost-effective EUV sources for lithography. It will be a key enabler of the technology, as the availability of reliable high-power EUV sources is the No.1 critical issue for Lithography. This research has the potential of enabling AMD's 22-nm technology node and those after that.

Research details: Development of a Predictive Modeling and Intelligent Decision Making Tools for High Yield Next Generation Semiconductor Factories University: Univ. of Michigan PIs: Ni, U of Michigan; Djurdjanovic, U of Michigan; Koc, U of Michigan

Technology Transfer: Research will help in organizing & aranging data with techniques not currently common in our industry

Impact statement: Research will address issues that are believed to be present in future manufacturing.

Research details: Prof. Ober, at Cornell

Technology Transfer: Fundamental knowledge molecular resists is very useful in order to assess 22-nm options.

Impact statement: If proven successful, these types of materials could enable 22-nm and beyond technologies at AMD.

Research details: This research develops efficient variational interconnect models to capture the impacts of multiple variations accurately over a wide perturbation range. Interconnect delay models can suffer from a dramatic growth in both the computational cost and model complexity as the number of variational sources increases. In this research, the PI's explore new means of building feasible models to include a large number of parametric variations. The variation-aware interconnect modeling can be used for SSTA tools.

Technology Transfer: With further scaling down the process technology, the process variations have a more important impact on timing analysis. SSTA becomes red hot as a possible solution for the larger and larger variations. Good delay modelings will be very important and indispensable to us if we use SSTA in our timing flow.

Impact statement: Statistical Static Timing Analysis is very hot in recent years to accurately and efficiently capture the process variations' impacts on circuit timing. Most approaches simply assume certain statistical delay models as input to the SSTA tools, which can introduce significant analysis errors. The modeling is actually as important if not more. This research fills the gap between SSTA tools and real circuits. It not only gives designers more accurate delay models, but guides SSTA researchers on how to define the input to their tools.

Research details: Circuit Primitives for Regular Logic Bricks

Technology Transfer: Regular logic bricks, or similar techniques is likely to be used in future microprocessors.

Impact statement: Recent advanced integrated circuit processes require increased geometric regularity. These logic bricks will help us achieve this regularity with a variety of design methods.

Research details: Reliability study for Cu/ultra low-k interconnect system.

Technology Transfer: This task is in its first year, and we anticipate to transfer new methodology and fundamental understanding of thin-film characterization and reliable advanced BEOL system.

Impact statement: This task will develop advanced surface and interface characterization methodology, and address the impact of surface/interface properties on BEOL reliability for 32nm and beyond technology nodes.

Research details: Thermal management in mobile processors

Technology Transfer: Wayne Burleson is working on lightweight thermal sensor design, which has proven to be an increasingly critical issue in designing power-effecient processors.

Impact statement: This research is just beginning, so there have not yet been any direct impacts. But they have a very well-defined direction and are receiving regular cooperation from their liaisons.

Research details: Ringo, Washington State: Entire CDADIC program

Technology Transfer: Introducing new circuit techniques extends the use of analog EDA tools, of great importance to Cadence's analog suite of tools. Cadence's Design Services does contract design on Analog, Mixed Signal & RF and the preparation of design kits to accompany these tools. Three areas of CDADIC research are particularly important: Data Converters — DACs & ADCs, Frequency Generators — Oscillators & PLLs, and ESD and Reliability structures

Impact statement: Over a number of years, the Analog/Mixed Signal design techniques developed under the CDADIC program have been critical to Cadence's success in designing these circuits.

Research details: White & Daniels, MIT: Synergistic Techniques for Extracting Accurate Wideband Models of Complex Interconnect for Mixed Signal Applications

Technology Transfer: Both in IC chip design and in the design of packages and boards, accurate, efficient models of interconnects are essential. Cadence's EDA tools in both these areas benefit from this leading research in computationally-efficient modeling of interconnects over wide frequency ranges.

Impact statement: This research is of continuing importance both to chip design and package/board design Cadence tools

Research details: Moon & Mayaram, Oregon State: Low Voltage PLL Design Tolerant to Noise & Process Variation

Technology Transfer: Achieving good performance of analog circuits such as PLLs is challenging at low supply voltages and increasing process variations. This project and CDADIC projects under #933 provide Cadence's custom circuit design group valuable help in meeting these challenges

Impact statement: Cadence has made continual use of these developments in its custom circuit design business

Research details: Roychowdhury, Minnesota: Fast Simul. of Data & Coupled Noise in Oscillators and PLLs via Nonlinear Macro & Multi-time Num'l Methods

Technology Transfer: Has been very helpful in equipping Cadence's Analog Simulation product SPECTRE to meet the difficult challenges of simulation Oscillators and PLLs.

Impact statement: Significant value in enhancing Cadence products.

Research details: Harjani, Minnesota: High Speed Clock & Data Recovery Circuits

Technology Transfer: Harjani's developments in injection lock dividers and clock recovery are put to use in Cadence's custom design of state-of-the-art circuits

Impact statement: Cadence has made continual use of these developments in its custom circuit design business.

Research details: Mayaram, Oregon State: Modeling & Analysis for Substrate Noise Mitigation

Technology Transfer: Cadence's custom circuit design group uses the results of this research extensively in reducing the noise effects on sensitive circuits due to substrate noise coupling.

Impact statement: Cadence has made continual use of these developments in its custom circuit design business

Research details: Harjani, Minnesota: Wideband Frequency Synthesizer and Fast Hopping System Design

Technology Transfer: Harjani's developments in rf circuit design are put to use in Cadence's custom design of state-of-the-art rf circuits.

Impact statement: Cadence has made continual use of these developments in its custom circuit design business.

Research details: Bryant, CMU:

Technology Transfer: The research from this and previous CMU projects is becoming more and more critical for good performance in formal analysis

Impact statement: Progress in Formal Analysis and Verification has been driven by university research such as this at CMU.

Research details: Cheng, UC Santa Barbara: System Level Verification by High-Level Satisfiability Checking

Technology Transfer: Cheng's past work in this area has been very important in enhancing Cadence's Verification products. Tim Cheng maintains arguably the top open ATPG engine, this has proved very useful to Cadence for benchmarking

Impact statement: Current and past research is this area has been very important

Research details: Somenzi, Colorado/Boulder: Procedures in Model Checking

Technology Transfer: Cadence uses CUDD and VIS in our formal analysis tool (IFV), developed under the previous project 920.001. The current project, 1365.001 promises equally important developments.

Impact statement: This research, over several years, has provided significant help in enhancing Cadence's Formal Verification tools, and is expected to provide important additional insights.

Research details: Clarke. CMU: High Level Design Verification

Technology Transfer: Clarke has been the leader for many years in development of theory and algorithms in Formal Verification, including the prior 1027.001 project of the same name. This project continues that important work to Cadence

Impact statement: Very important to Formal Verification

Research details: Chew, Illinois/Urbana: Fast Algorithms for Crosstalk Analysis

Technology Transfer: Cadence is investigation the potential of the software MFIPWA (Modified Fast Inhomogeneous Plane-Wave Algorithm) for enhancing the EDA tools for the design of ICs, Packages and Advanced Printed Circuit Boards as they are used to minimize crosstalk.

Impact statement: In early stages of investigation, this has potential to improve Cadence's EDA tools for the minimization of crosstalk.

Research details: Xie, Portland State: Scalable Co-Verification Based on Hardware IPs & Software Components

Technology Transfer: Potential for attacking difficult hardware/software co-verification problems

Impact statement: High potential for enhancing Verification products

Research details: Hsiao: Virginia Poly: Partitioned Search State Coverage for Coverage-Directed Stimuli Generation

Technology Transfer: Could significantly enhance ATPG EDA tools in developing efficient test patterns

Impact statement: Significant potential for attacking difficult Verification and Test Generation issues

Research details: Rosenbaum, Illinois/Urbana: Simulator-Independent Models of ESD-Protection Devices

Technology Transfer: Cadence provides design services to customers in the most difficult design areas. ESD protection of the highest speed circuits has not been properly addressed by industry. Her research is particularly useful in getting the high speed of the process realized in the chip's I/Os. This project continues the good work of 955.001

Impact statement: Tools to design I/O pads resistant to ESD but also applicable to high speed connections are urgently needed.

Research details: Process Aware EDA Toolkit - Neureuther, UC Berkeley

Technology Transfer: Neureuther's past research, such as the California MICRO project "Feature Level Compensation & Control" have been productive to Cadence and provide a good start for this SRC project. Just starting, this new project may give key insights into how to couple EDA design tools to DFM requirements.

Impact statement: The research is forward looking and promises to significantly enhance Cadence' s EDA products n the future.

Research details: Brayton, UC Berkeley: Innovative Sequential Synthesis and Verification

Technology Transfer: A recently initiated project, this has high potential in enhancing Synthesis and Verification technology

Impact statement: High potential

Research details: Specifically 425.021 Low-Water and Low-Energy Rinsing and Drying of Patterned Wafers, Nano-Structures, and New Materials Surfaces with Bert Vermeire and Farhang Shadman

Technology Transfer: This project is to develop sensors that tests the wafer surface chemistry during wafer rinse. This is more accurate than measuring the rinse bath ph and chemistry. As part of testing one of their prototype sensors, we have seen very interesting data that is very suggestive of substantial cost savings through reduction of DI water usage.

Impact statement: The rinsing of different chemistries can be costly and difficult to optimize, particularly as geometries shrink. New rinses can be developed much more efficiently and transferred to wafer fabs much more easily with substantial cost savings.

Technology Transfer: This technology is of future and strategic interest for CMOS scaling and interest exists to transfer this into Freescale.

Impact statement: Ge is a strong contender for next generation CMOS. Based on their earlier work on III-V surfaces, the Kummel group has a strong and unique expertise in oxide/semiconductor interface preparation and analysis. They developed a method of reliably preparing unpinned Ge(100) in UHV. This is critical to any Ge MOSFET.

Research details: Development of abrupt junction technologies based on recessed source/drain etching and selective epitaxial growth of doped silicon and silicon germanium.

Technology Transfer: Feasibility demonstration of recessed source/drain etching and selective epitaxial growth of doped silicon and silicon germanium.

Impact statement: This technology has been instrumental in allowing continued device performance increases in the face of an inability to scale gate oxide. Along with task 1137, this task also led to the development of uniaxially strained PMOS device technology based on selective source/drain epitaxy which has been widely adopted throughout the industry.

Research details: Tasks from 532, 539, 677, 707, 1017, 1081 and 1372.

Technology Transfer: Through a series of SRC funded research projects (including 532, 539, 677, 707, 1017, 1081 and 1372) the FLOOPS process simulator and a series of increasingly advanced models were developed. A version of the code was commercialized by Integrated Systems Engineering and is available today.

Impact statement: The FLOOPS process simulator is widely used in Freescale for advanced transistor design. Its model scripting language (Alagator) provides ongoing opportunities for rapid adoption of new models from Florida into a robust simulation environment suitable for future transistor nodes.

Technology Transfer: There are several interesting outcomes: (1) The use of C-containing buffers to improve the epitaxial quality of Ge on Si. (2) Selective epitaxy of Ge and related alloys on Si. (3) Gate dielectrics for Ge MOSFETs and their performance. (4) Energy-filtered TEM analysis of Ge and Ge:C on Si. An internship and at least one joint publication on ellipsometry and TEM analysis of Ge:C alloys on Si solidified the transfer of this group's knowledge to Freescale.

Impact statement: The research group developed processes and characterized the materials to form Ge-on-Si pFETs that had greater than 2X peak mobility enhancement over the silicon control samples. This work defined the limits of p-channel engineering, guiding our own choices for future technology nodes. These students are especially well trained as either integration or device engineers.

Research details: Tasks 1139 (Ma, Yale University) and 616 (Osburne, North Carolina State University)

Technology Transfer: These tasks provided performance data on many dielectric materials systems that were not available 'in-house'. Certain Hf-based dielectric systems were identified for further study in-house.

Impact statement: Alternate high-k dielectrics are of great interest as CMOS devices continue to be scaled. Epitaxial semiconductor/high-k systems may yield the opportunity to achieve improved device scaling and performance through atomic level control of interface bonding.

Research details: Tasks 1142 (Garfunkel, Rutgers University)and 616 (Osburn, North Carolina State University)

Technology Transfer: These tasks asssisted in the development of conceptual tools and physical characterization methods that have helped to clarify the basic science behind effective work function measurement and engineering. Some metal gate systems were identified for further study at Freescale.

Impact statement: Metal gate electrodes are of great interest for future CMOS technology generations. Information gained from this task provided additional insight into the interface mechanisms that influence the work function and how charges in the gate-stack affect the 'device measured' effective work function. Ultimately, this information is used to determine which gate stack configurations will yield the best performance.

Technology Transfer: With the recent completion of the project, the new Monte Carlo device simulation software was transferred and successfully tested internally.

Impact statement: Software provides unique ability to simulate hole transport under strained conditions for realistic short channel MOSFETs. The software is expected to greatly benefit CMOS process development by providing an understanding of the most effective and scalable stressor combinations. Has already been used to confirm continued benefits of scaling current PMOS stressors. Also, expect to be able to use software to test the benefit of some specific novel stressor ideas before fabrication. Note, will continue to be developed with support from a new TI custom-funded project, 1452.001

Research details: The researchers have implemented a timing simulation framework where timing models are statistical. This framework is being used to investigate the effects of process variation on chip timing. We have teamed with that group to use their research results on a sample of our chips.

Technology Transfer: This group has produced several novel methods for correlating the results measured on silicon with a pre-design statistical simulation framework. Several students have interned with different DTO groups last summer as well as in 2004 and 2005. The PI visits FSL regularly to talk to the various teams. Several publications were produced or in the pipeline, and the research is influencing our SSTA, test and DFM methodologies.

Impact statement: This research is very crucial to our understanding of how process variation can be effectively modeled and how the results correlate with the actual silicon results. The impact is enormous on our ability to design and optimize chips in the presence of process variation. It also affects our yields, our ability to do binning, distinguish between defective chips and normal process variation distributions.

Technology Transfer: An electromagnetic bandpass (EBG) bandpass filter technology available as either a discrete or integrable device.

Impact statement: Filters play an increasingly important role in multiband microwave communications systems. Existing discrete bandpass filter technologies are seen by many as limiting the size, cost and levels of integration for these systems. Filters constructed using EBG metamaterials are potentially smaller and more easily integrated than existing discretes, and may be an attractive alternative.

Technology Transfer: We have successfully transferred an IQ mixer, high output power, high linearity PA pre-driver amplifier and DVGA. In addition we brought the Ph.D. student from this project here as an intern this past summer.

Impact statement: Project is the first to achieve +10dBm output power with high linearity for WCDMA transmit applications with all CMOS through the use of predistortion techniques that are new for this application.

Research details: Placement of On-Chip decoupling Capacitors

Technology Transfer: A design methodology for placement and sizing of decoupling capacitors at the local and chip level was transferred to Freescale. Much of the work was done through summer interns in 2005 and 2006. - University of Rochester submitted two SRC patent applications; both are filed. - There are several IEEE papers published, and more to come.

Impact statement: A design methodology for placing and sizing on-chip decoupling capacitors has been developed. The research clearly showed that current methodologies for inputting decoupling capacitors are inefficient and may degrade performance. These models can be integrated into a flow based on a library with a current profile characterization of the substrate, thereby optimizing power/ground noise of a circuit, one of the more increasingly difficult design problems of large-scale mixed-signal circuits.

Technology Transfer: An intern developed the lithography aware cell characterization flow during the summer of 2006. He established a clean and reusable flow within the framework/suite of FSL backend tools.

Impact statement: The research demonstrated a productive simulation tool and flow to link multiple sources of lithography variability on performance metrics. A production flow has been developed within FSL for characterizing standard cells considering lithography parameters. The methodology has helped FSL understand the impact of systematic components like standard cell neighborhood structures on cell timing. An analytical model that captures the impact of focus variations was developed. We are evaluating the models on FSL technology in preparation for incorporation within the FSL statistical timing analysis engine.

Technology Transfer: Technical transfer of 3D fracture mechanical software, FRAC3D, can include the executive file, basic example, more practical examples, a user manual, and the software code if desired.

Impact statement: Delamination and cracks are among the THE MOST COMMON mechanical issues in semiconductor packaging. These issues directly impact product quality as well as product development through issues such as low-k die crack. This project is not only practical, but also very challenging. Stress singularity at the crack tip, 3-D fracture structure and multi-material interface, as well as the critical local thermal stress are often impacted by a structure which is larger by many orders of magnitude. With many years of substantial progress, Dr. Nied and his team have produced FRAC3D which combines the strength of commercial FEM software (such as ANSYS) and the application of a special tool to provide practical fracture mechanical analysis and solutions.

Technology Transfer: Through the measurement of circuits designed by Prof. O's student, who interned with us, Freescale found a potential problem of the measurement setup. This triggered a more thorough study of the measurement procedure.

Impact statement: This group has very good experience in designing millimeter wave circuits using CMOS. Their work on RADAR circuits allows Freescale to understand the potential of CMOS in this market without investing too many resources prematurely internally.

Research details: (1) Investigate effects of scaling and material processing on the reliability statistics and failure mechanisms for EM and SM of Cu/low k interconnects (2) Explore key factors limiting the reliability of future Cu interconnects, including air-bridge structures and 3D interconnects

Technology Transfer: The results obtained at Prof. Paul S. Ho's research lab at UT Austin will be used for future technology applications at the C45, C32, and beyond nodes. Some of the most important technologies for future interconnect systems will be the use of metallic, electroless coating processes of Cu lines. This specific process has been characterized very well through stress-relaxation experiments that clearly show the superior behavior of e-less overcoats. Furthermore, this research task investigates the electromigration scaling behavior. The ITRS roadmap currently predicts line dimensions of about 60nm in the 2008 timeframe. The UT Austin lab, in collaboration with SEMATECH, has fabricated lines of this dimension already in 2005, and has tested these lines for EM reliability, with very encouraging results. Furthermore, the scaling behavior of Ta-based barriers has been assessed. These major items are expected to be vital parts of future technology transfer.

Impact statement: The impact of the work done at UT is very significant. Prof. Ho, as he has done in the past, precisely identified the most important issues of future interconnect systems. The main electromigration diffusion path, namely the top interface between Cu and passivation, needs to be strengthened through the use of electroless, metallic overcoats. Furthermore, the reliability scaling behavior for very fine lines needs to be assessed. This has been done through a very elaborate study using backfill processes. This way, the UT group was able to perform a good look-ahead for future process generations.

Research details: PSP Compact MOSFET Model Development

Technology Transfer: New and improved capabilities in the PSP MOSFET model, to enable much higher accuracy CMOS IC design, especially for Analog and RF. SRC support enabled PSP to become the best MOSFET model developed and is the platform we and other companies are expecting new developments to be delivered in. We have used its predecessor, SP, successfully for years in critical RF product designs and are in the process of migrating to using PSP as our standard MOSFET model.

Impact statement: Appropriate SRC funding of this new industry standard MOSFET model will significantly enhance design capability. As CMOS technologies advance, previously unknown or unimportant effects can suddenly become showstoppers, hence continued development of MOSFET models is critical. Specifically, modeling of proximity effects and lateral nonuniformity in channel doping are critical to address circuit failures we have seen. Improved noise and RF parasitic modeling is also key, as is integration of statistical variations within the core model. These are all priority items on the SRC task for PSP improvement.

Technology Transfer: Development and potential transfer of process conditions for the growth and annealing of Ge-rich strained Si/strained SiGe heterostructures for dual channel devices. Two joint papers have been published with Freescale.

Impact statement: This research addresses the issue of asymmetric carrier mobility between NMOS and PMOS devices by utilizing Ge-rich channels with concentrations ranging from 0.5-0.8. UV-Raman spectroscopy confirms that the HOI structure can be transferred to the insulator for ultra-thin body devices while maintaining channel strain and carrier mobility.

Research details: The relevant task is 1292.007 - T.S. Kuan. This research has been focused on understanding and finding solutions to increasing copper resistivity with line scaling.

Technology Transfer: This work is providing us with fundamental understanding of the limitations and potential improvements to copper resistivity for future technology nodes to 22nm.

Impact statement: Copper resistivity scaling is one of the most important challenges for future interconnect designs. This work is helping us to understand the fundamental limits and to identify potential improvements. The researchers' collaboration with Sematech, equipment suppliers, and other industrial liasons has also maximized the impact of their work.

Research details: Multiscale Modeling of Dopant Profiles with Improved Defect-Dopant Dynamics Models

Technology Transfer: Advanced Arsenic diffusion and clustering models implemented in kinetic MonteCarlo (kMC) simulator and code transferred to Freescale. Calibration experiments designed to highlight the most critical parameters of Arsenic models have been performed at Freescale by summer intern/ UT/Austin SRC-student. Freescale have applied kMC modeling of Arsenic pile-up at interface and redistribution to understand the effect of post-implant thermal cycles and Si recess on variation of device performance across the wafer. We also applied these modeling and experimental results on defect engineering to achieve shallow n-type junctions what will effect several technologies.

Impact statement: As device dimensions shrink, interface-related models as well as modeling of process-induced strain become crucial in building new generation of process simulation models and tools. We cannot approach these problems through experimentation. The focus on developing fundamental understanding of n- and p- type dopant as well as point and extended defects behavior at Si/SiO2 and strained Si systems combined with their cutting edge and inherently multi-scale approach will enable us to explore properties of the interface and strained systems not accessible by other means. Realistic structures of amorphous-crystalline interface as well as extended defects in the UT/Austin developed bond switching simulator are critical to our addressing key process problems.

Technology Transfer: A novel process methodology for the wafer-level packaging of MEMS structures is being developed. Freescale's feedback and direction was considered highly in the planning stages. The UTA team has worked very hard to accommodate all of our requests. Biweekly meetings are being held to monitor progress. We will initiate a number of efforts to leverage this technology once the prototypes have successfully completed reliability testing.

Impact statement: Dr. Butler's team at University of Texas, Arlington is working on developing a self-packaged wafer-level process for MEMS devices. In the past four months since this project started, the team has identified two main packaging schemes, performed simulation studies to accurately identify any issues with their integrity, and are currently finalizing layout of packaged MEMS resonators for fabrication. Dr. Butler and her student have shown exceptional ability to get up to speed and detail to attention in this project. This new methodology could potentially result in a disruptive, low-cost, high-throughput packaging for the MEMS industry.

Research details: Objectives: characterization of systematic and random within die variation and incorporation in cell libraries.The models will be used for timing and power dissipation analysis. The simulation flows will include analysis of process corners of systematic variation combined with statistical simulation for the random component.

Technology Transfer: We are very interested in the objectives & deliverables of several SRC tasks that would have a large impact on our Statistical Static Timing Analysis tool and design methodologies and libraries. This particular task is one of the stronger ones.

Impact statement: This task will likely have a strong impact. It will enable design on technologies with process variation by: 1) Design, measurement techniques and data analysis of test structures that will characterize layout-dependent effects. 2) Characterization and generation of the compact models and pre-characterization for systematic variations, including incorporation of this information in cell libraries through sensitivity functions. 3) Implementation of a statistical timing analysis tool.

Research details: Excellent work of Paul Ho on electromigration in flip chip inrercinnect using High-Sn solder has finished timely with our starting to see the same problems Ho studied, on our products in development. The foundation this work provides will be invaluable in our ability to find workable solutions at our company.

Technology Transfer: Although this work was believed to be important, it is only after seeing the conclusions reached during the study, and recognizing how this can be applied to our current development problems, that the value was fully recognized. The full TAB sensed this even, though we do not have a specific continutation of the is project funded at this time. Pb-free flip chip bumping will require resolution of this challenge.

Impact statement: Although this work was believed to be important, it is only after seeing the conclusions reached during the study, and recognizing how this can be applied to our current development problems, that the value was fully recognized. The full TAB sensed this even, though we do not have a specific continutation of the is project funded at this time. Pb-free flip chip bumping will require resolution of this challenge.

Research details: Duaskardt has been studying interfaces properties for materials set of interest to packaging for some time. In a series of projects, his team make ongoing progress in advancing the state of the art in this critically important aspect of packaging science.

Technology Transfer: We have had ongoing industry liaisons with Dauskardt through the years, which has been fundamental to our value extraction. Excellent annual contract reviews, with always superb student presentations have been a mainstay for transfer.

Impact statement: On several occassions, insight provided by this work has had direct applicability to problem solving at our company, typically in interface integrity. Measurements techniques have been duplicated and have aided directly in materials selection.

Research details: Optimal Receiver for 20GBPS Serial I/O Links; UCLA Task Leader: Chih-Kong Ken Yang

Impact statement: Current high-speed serial link are typically designed for up to 11 Gb/s over legacy backplane channels with up to 30dB attenuation. Future products, driven by customer demand, will have to operate at 20Gb/s data rates and above. Achieving 20Gb/s operation over the same channels would require processing high-speed signals attenuated by as much as 40dB. This is a formidable research challenge, as no cost-effective solution to that problem is known at this point. Prof Ken Yang's research directly adresses this difficult problem.

Research details: Feasibility of Implementing CMOS RF Front-End Circuits for 76-77 GHz Radar Applications; U of Florida Task Leader: Kenneth K. O

Impact statement: IBM is actively pursuing the millimeter-wave application space in silicon technology, specifically for high data-rate 60GHz wireless communications. We have done extensive work in this field using silicon-germanium BiCMOS technology (IBM's 8HP). We are very interested how the performance of CMOS will compare with advanced SiGe. Also we are very interested in the vehicular radar application space. Ken O's work at the U. of Florida fills both of IBM's needs, and in one year, they have already accomplished quite a bit with the demonstration of some critical building block circuits at 77GHz in 65nm CMOS technology from TI.

Research details: In this relatively new project, Suo takes an unusual and interesting look at the increasingly important interface between packaging and back end structures and processing. I've no doubt that this fresh view will lead to useful insight in years to come.

Technology Transfer: New contract...in process of establishing liaisons. Transfer limited to first annual contract review...less than a year underway.

Impact statement: With back end materials going to ever lower dielectric, we anticipate continuing decline in mechanical properties which, when assembled into a package, will generate stress vs strength issues. Understanding of these fine interactions will be critical to solving the chip-package interactions challenges of ultra low-k

Technology Transfer: Quarterly review and tele-conference to member companies

Impact statement: The development of MBE grown high k ternary oxide is critical to engineering of novel dielectrics on Si and high mobility channels. The Penn State work has paved ground to fabricate new gate stacks for 22 nm devices; the program has proven very useful since it started in 2003, and continues to yield useful insights on the potential of extending CMOS using III-V channels.

Research details: Extension of Displacement Measurement Techniques into Nano-Mechanics Domain

Technology Transfer: This work allows measurements of displacement down to the nm scale.

Impact statement: As technologies scale, nm resolution metrology is needed. This work addresses this issue.

Research details: Closely related to 1129; our comments refer largely to materials aspects at Penn State, but characterization and device work at UCSB and Yale are also valuable.

Impact statement: The development of MBE grown high k ternary oxide is critical to engineering of novel dielectrics on Si and high mobility channels. The Penn State work has paved ground to fabricate new gate stacks for 22 nm devices; the program has proven very useful since it started in 2003, and continues to yield useful insights on the potential of extending CMOS using III-V channels.

Research details: Exploring NoC topologies and interconnect optimized for power and area

Technology Transfer: An algorithm on rebalancing interconnect was applied to reduce and eliminate hot spots in Merom and Yonah

Impact statement: Today the result was used to tweak wire layout to resolve hot spots. NoC topologies and interconnect knowledge will become even more critical to explore many core design space.

Research details: Develop a physics/stochastic device/process model for real-time process/ factory optimization and control; develop a multi-step EPC strategy that performs optimizations of input targets for a lot being processed; explore and integrate the intrinsic properties of disruption management in the semiconductor fab

Technology Transfer: Two students served as Interns at 2 member companies. Regular meetings held with members from 4 member companies. Plans in place to develop EPC models that will be transfered to member companies.

Impact statement: Currently, fab-wide control model does not exist and they are one of the solutions projected by ITRS Factory Integration for effective and efficient lot and factory management. The idea is to go from Tool level to Layer level to fab-wide control. PIs have developed a multi-step control algorithms that is being tested. They have also developed a PLS model based on simulation and published survey analysis that provides information of various fab disruption.

Research details: Directed Self-Assembly (DSA) at Wisconsin, Stanford, MIT, etc.

Technology Transfer: While this revolutionary technology (~ 10 years out) has not yet penetrated R&D activities with chipmakers, it has on the other hand caught the attention and imagination of researcher to watch ongoing progress and provide constructive inputs.

Impact statement: Good progress has been made to date to demonstrate nested & isolated lines, elbows and jogs as fundamental patterning building blocks. First real impact likely in memory and perhaps logic later

Research details: The current research thrust of directed self-assembly represents a very innovative approach to patterning on the nanoscale.

Technology Transfer: I would call it knowledge transfer not technology transfer, as most chip makers are just absorbing the information while providing feedback.

Impact statement: Nealey has demonstrated more random features recently, showing that progress in this field is encouraging. There is no direct impact for chipmakes since the technology is probably still 10 years out.

Research details: UCB Project: Frechet novel non-Chemically Amplified Resist

Technology Transfer: This project conceives of a new concept to engineer photosensitive polymer chemistry that causes "unzipping" of chains that serves as a solubility switch.

Impact statement: This has signficant potential to address the current acid diffusion problem causing significant image blurring

Research details: The main goal for Maskless Droplet-on-Demand (DoD) Systems is to achieve maskless printing of ~ 50 nm features at low cost for a number of applications such as packaging, biotechology, low cost electronics, etc.

Technology Transfer: For now, the technology is too immature to be transfered to chipmakers, but much interest and mentor guidance exists especially in the packaging area.

Impact statement: Given the anticipated low cost for this technology significant potential exist in the low cost electronics, biotech, and packaging areas. The next 3-5 years will probably tell the story...

Technology Transfer: Capabilities developed for Ge and GaAs are now being applied to III-V systems as part of the new NCRC.

Impact statement: The combination of experimental and computational techniques to understand semiconductor/dielectric interface states has the potential to guide and enable the development of III-V MOS.

Research details: Explore a novel statistical framework for modeling and methodology for validation and "Si learning"

Technology Transfer: This project is still in the third year. Two very important ideas/methodologies could come out of this work eventually. One is to select test vectors based on Post Si "model tuning" and second is how to test adaptive features based on Si learning.

Impact statement: We currently rely heavily on system level test and a huge amount of vectors from different groups (SV, CV, AV...) to validate Si, many times overlaping or have holes in coverage. Efficieny and Coverage will be greatly enhanced if we have a systematic technique to pick just the neccessary tests. Testing of adaptive features on Si (such as power up/down, reconfigurable cache...) has been identified as one of the most challenge task without any good solution. This project can lead to one efficient way to overcome.

Research details: Interfacial Chemistry and Atomic-Scale Reactions in Ultra-Thin and Zero-Thickness Barrier Layers for Cu Interconnect Prof. Muller Cornell Univ Novel quantitative measurements of Cu interfacial reactions using atomic-resolution EELS (similar to very successful 3D EELS metrology task 1105). New characterization methods for ultrathin barrier layers to help integration of new materials.

Impact statement: New capability providing microscopic understanding of the interfacial chemistry and bonding between Cu interconnects and very thin liners - at close to atomic resolution. This is important to allow systematic development of new materials and interface optimization to increase adhesion and electromigration resistance.

Research details: Pure Silica Zeolite Low k Films

Impact statement: Potential material with both low k <2.0 and strength E>10

Technology Transfer: Too early for this specific project, but Purdue has an excellent track record of enabling use of the capabilities they develop by industry and other researchers via the Nanohub.

Impact statement: Developing the next generation of device modeling capabilities that will make modeling of quantum transport effects feasible.

Research details: Using power grid and power pin to carry modulated test data in and out

Technology Transfer: This project is in the first year exploring feasibility of the idea.

Impact statement: Future multicore processors will greatly limited in pin count, impacting the observability and controllability for testing these products. If successful, this project provides one solution to clock test data in and observe results all on "free" power pins.

Research details: III-V MOSFETs for sub-22 nm Scaling - High-k Dielectrics

Technology Transfer: Quarterly review and tele-conference to member companies.

Impact statement: The high k / III-V MOSFET research at UCSB will identify key challenges and may provide solution paths to 22 nm logic devices and continue to enable CMOS scaling.

Research details: Power-Performance Tradeoffs in ASICs

Technology Transfer: This project focuses on the power-performance optimal design of ASICs using gate sizing, and supply and threshold voltage optimization. The sensitivity-based optimization will be used to optimize the benchmark circuits, such as arithmetic-logic units, floating point units, FIR filters and Viterbi decoders within conventional ASIC design flows. The exploration starts with combinational logic blocks and extends to pipelined logic. Our goal is to optimize the gate sizing/wire-load ratio, flip-flop/latch selection and pipeline depth. We further plan to use this methodology for extending the design space by using the multiple supplies and threshold voltages.

Impact statement: Power-Performance trade-off techniques are required in all applications used by LSI Logic: high end: storage/networking, low end: consumer. This research is very promissing to address the major reliability, design integrity, and cost issues caused by the increase of power consumption in SoC. process selection (multi-well technology, SOI), cell design, chip level optimization, system level power budgeting.

Research details: Environmental Health & Safety Task ID 425012 and 425013

Technology Transfer: Develop methods to quickly assess possible EHS impacts of new chemicals. Development of non-PFOS lithography materials.

Impact statement: Ensure the development and selection of new process chemicals which have minimal adverse EHS impacts.

Research details: Circuit Optimization for Low Power and High Speed in the Presence of Uncertainty

Technology Transfer: This proposal will develop techniques for analyzing and optimizing the major performance parameters (timing, power, and variability) under manufacturing and environmental variations. Leakage power, in particular, will be a growing contributor to the total power, and solutions will have to be developed not only to control subthreshold leakage, which is already a problem for high-end designs, but also gate leakage. Variability is an important factor for optimizing timing and leakage power and will be considered as an integral part of the optimization. Our objective is to develop fast and efficient techniques to (a) measure the impact of process variations on performance parameters; (b) evaluate environmental variations by developing fast engines that model temperature and IR drop variations (c) relate environmental variations to circuit performance parameters; and (d) perform variability-conscious circuit optimizations to meet power, timing and signal integrity co

Impact statement: The ongoing/future plan is to optimize all parameters that contribute to the power consumption within a cell: manufacturing variations, which alter the values of parameters such as transistor widths, lengths, Vt and tox, and environmental variations which change the operating context of a manufactured circuit due to fluctuations in on-chip temperature in different operating modes, or due to injected noise, and changes in the supply voltage. LSI Logic having a wide product portofolio has to provide multiple libraries to meet the requirements of the different applications, including the power requirements. These techniques will help to generate a more power-aware library set, without compromising other areas like performance and density.

Technology Transfer: Development of high speed I/O built-in self-test system to efficiently measure jitter in high speed differential signals with pico-second accuracy will be useful to LSI.

Impact statement: Customers are demanding higher levels of built-in diagnostics in high speed serial interfaces. These diagnostics include circuits such as jitter measurement This work is directly help LSI's ongoing efforts in these areas.

Technology Transfer: This research has demonstrated the fundamental capability to extract defect density and size distributions from failing vector data on scan based tests. However, there are two reasons we are not able to take advantage of this technology today. 1. The current approach only consider bridging type defects and neglects open type defects. This is problematic for two reasons. First, opens are a major defect class in Cu technologies and is necessary to complete the defect pareto. Second, the researched technique relies heavily on the selection of defect mechanisms included in the distribution extraction. Without the consideration of open defects, it is likely that the bridge results are not accurate. 2. For a fables company, makes this a valuable technique without access to fab data. However, foundries do run test chips to obtain this data and it is now being provided to foundry customers in encrypted format. There now exist tools to use this

Impact statement: The extracted data is a valuable for performing DFM, yield and DPPM analysis and the technique provides the unique opportunity to obtain this data without the need for costly test chips.

Technology Transfer: - Many problems cannot be solved with pre-silicon model analysis. Some information is much easier to get from silicon samples - This project incorporates silicon learning - Allows testing in the midst of process variations, crosstalk, small defects, thermal effects etc.

Impact statement: 45nm designs will see these situations and some of these techniques coming out from this research will be useful. Statistical methods are key for future tests where variations in process, test mode characteristics etc may be difficult to account for in timing.

Technology Transfer: There is a need today to minimize scan delay test pattern qualification time due to false and multi-cycle paths. The results from this research can be applied to generate more effective delay patterns and reduced pattern qualification time.

Impact statement: The result of the research will have future impact to LSI in enabling quality improvements and meeting more aggressive DPM requirements.

Technology Transfer: Efficient and cost effective test is key to reducing both the 1-time test pattern generation cost, which is quite high, for delay fault patterns [newer fault models will require additional targeted pattern generation and this will add to the overall pattern generation time] as well as the recurring test application cost. Yield Loss minimization is key as well and this research focuses on these 2 aspects, which are considered key by LSI. Some of the techniques to improve run times have been implemented in atpg tools that we use.

Impact statement: Any reduction in overtesting will help to reduce yield loss

Technology Transfer: Efficient and cost effective test is key to reducing both the 1-time test pattern generation cost, which is quite high, for delay fault patterns [newer fault models will require additional targeted pattern generation and this will add to the overall pattern generation time] as well as the recurring test application cost. Yield Loss minimization is key as well and this research focuses on these 2 aspects, which are considered key by LSI. Some of the techniques to improve run times have been implemented in atpg tools that we use.

Impact statement: Any reduction in overtesting will help us to reduce yield loss

Technology Transfer: We do not personally see a lot of value we can gain from this research. It is possible that EDA atpg tool developers can gain additional insights into their bridge candidate filtering, based on this research.

Impact statement: Possible improvement to quality and DPM improvements.

Technology Transfer: Package modeling is critical to developing high performance ASIC products. The ability to provide accurate high speed models has strong potential.

Impact statement: Characterization of packages, both with external signal sources such as time domain reflectometry (TDR) and S-parameter measurement, as well as with internal sources, will produce results that are of immediate benefit.

Technology Transfer: It is believed that some of the new concepts developed in this task will help address some of the more complex modeling issues that are involved in predicting and more accurately modeling various sources of static power dissipation.

Impact statement: Static power together with dynamic power is quickly becoming one of the most important design issues after performance goals are met. The percentage of the total chip power consumed by static power draw is dramatically increasing on ASIC and standard products with ultra deep sub micron technologies. After timing is closed, everything that can be done must be done to reduce power to save on package and system cost. Developing more accurate estimates of component sources of static power draw is the key to reducing risk for potential package thermal dissipation issues and staying within required power/thermal budgets.

Technology Transfer: It is believed that some of the new concepts developed in this task will help address some of the more complex modeling issues that are involved in implementing sleep transistor power methodologies.

Impact statement: With any sleep transistor method of power gating there are modeling issues involved with area, power estimation and sizing, noise, on chip capacitance estimation, and power up and down time modeling issues that need to be addressed to ensure successful chip level implementation. It is anticipated that this task will aid in the development of some of those models and estimation techniques.

Technology Transfer: It is believed that some of the new concepts developed in this task will help address some of the more complex modeling issues that exist with cureent source modeling techniques.

Impact statement: As LSI Logic continues to move forward with current source modeling efforts, this SRC project will help fine develop more sophisticated statistical models and model extensions.

Technology Transfer: It is believed that some of the new concepts developed in this task will help address some of the more complex modeling issues that exist with current SSTA techniques. It will be recommeded that a liason be appointed for this task.

Impact statement: As LSI Logic continues to move forward with SSTA, this SRC project will help fine develop more sophisticated statistical models and techniques to address older 2^N pessimistic corner analysis techniques.

Research details: Optimization of Lithographic Induced Variability for Improved Circuit Performance Task ID: 1226.001 Start Date: September 2004

Technology Transfer: A method to characterize the impact of cell placement due to differences in layout context has been developed. While minor differences are expected for large technology nodes. Larger differences are expected for smaller feature sizes, where process variability becomes an important contributor to pattern transfer. The evaluation of smaller features sizes has been due to the inability to share real process information with the University.

Impact statement: The analysis of libraries are a fundamental first step towards a process-variability characterization of standard cell design. With the results of this research it is possible to plan and validate internal findings that suggest the types of tools and methods that could be employed to arrive to less sensitive layout configurations, or systems that are able to identify such structures and limit the overall impact in chip performance and power utilization.

Research details: The CAIST

Technology Transfer: Novellus continues to recognise the value of the CAIST as a one stop shop for interconnect research, that focusses primarily on the extension of copper low k technology. Transfer is achieved via our assignee to Albany and by diligent mentoring of key programs.

Impact statement: Critical research and student development that can continue to help us provide state of the art interconnect technology for now and for the future. The work covers many critical aspects of the technology; deposition; interactions; CMP; structures; modeling; interactions; and reliability.

Research details: This is the work of Professor David Graves at Berkeley. Plasma surface interactions with ultra-low k materials; investigation of ULK damage. The work uses a combination of process equipment and metrology.

Technology Transfer: This program matches our internal interests in the plasma/low k area very well. It leads nicely into understanding the interactions between the low k materials and beams of reactive atoms like oxygen, hydrogen and nitrogen or various beams of radicals such as Ar+, Xe+ and Oxygen. The results impact process development for the application of ULK materials; particularly their susceptibility to damage from etching or surface cleaning.

Impact statement: This work is on going although the potential significance of the work has been realized for some time. The work is incomplete but is generating valuable information, particulalry the impact of oxygen on the low k films.

Research details: World class modeling capability by Prof. Kushner and his students, that has been ongoing for many years, but which continues to provide improvements to our ability to model plasma processes.

Technology Transfer: Technology Transfer of HPEM, DTS, MCFPM codes are continuous at Novellus Systems. All the codes are used throughout the company through our centralized modeling group. Most of the code capabilities are not found in current commercial codes on the market.

Impact statement: The research has been recognized previously and continues to provide significant value to Novellus Systems. The codes are heaviy used at all phases of product development. Simulation results provide process insight that is not currently possible through ordinary experimental means.

Research details: Extension of copper technology to the "end of CMOS". There are multiple programs funded largely through the CAIST which bear on the extension of Copper interconnect technology. The professors names are Kuan, Gall, Dunham, Coffey, Barmak, Dunn, Lifshin and West. Professor Dunham's program is a CSR program 1384.001

Technology Transfer: This work impacts a large part of the semiconductor industry; in that at this time we do not have a conductor that can be used for on chip interconnect that is better than copper, and copper itself is being impacted adversely by the shrinking dimensions of the interconnect. This compendium of programs provides reasonably comprehensive coverage of the key areas for research; scaling; electron scattering; modeling; grain growth; processing and barrier materials.

Impact statement: The work in these programs can help us extend copper to its ultimate limits. It is labelled for future impact because the work is recognised as being significant but the actual impact of the research is not yet on the table.

Research details: Meindl and Naaemi's work on the limits of interconnect as we currently understand it

Technology Transfer: This modelling work teaches us where to push for improvements and to better understand the limits of the technology we have today and hope to have in the future. It can lead the way towards necessary changes in design and architecture.

Impact statement: This work has major future impact, by addressing the impact of interconnect materials and geometry on our ability to keep the semiconductor industry on track with Moores law. The work will also help us recognize the needs for architecture or concept changes.

Research details: Tailoring NiSi Chemistry for WNx ALD: Oxidation, Precleaning, and WN Precursor Interactions, Jeff Kelber, University of North Texas

Technology Transfer: 1. Method for effective cleaning of NiSi salicided contacts in semiconductor manufacturing for improved contact resistance, Rc. 2. Integration of ALD WN advanced barrier with NiSi for filling of contacts.

Impact statement: NiSi contacts are in widespread use in logic devices. As the device dimensions shrink, precleaning of NiSi at the bottom of the contacts using conventional sputtering technology becomes increasingly difficult. As an alternative a chemical clean is being developed. For this to work, a good understanding of the nature of the oxide is important. In addition, in an advanced contact fill scheme, where barriers such as ALD WN are used, it is important to understand the integration issues that one might encounter.

Technology Transfer: Detailed surface analysis of the MOCVD PZT films has shown the existence of an excess layer of Pb on "as processed" films. Further analysis has shown this excess Pb layer reacts with the top electrode during deposition; removal (using an etch process) of the excess Pb layer prior to top electrode deposition results in a Pb deficient interface and relatively weaker reliability.

Impact statement: Additional experiments are in progress to quantify these effects using Iridium Oxide top electrodes, which correspond more directly to TI's process.

Research details: Prof. Gottlieb Oehrlein, U. Maryland, Model and Mechanisms of Plasma Surface Interactions and Surface Modification During Plasma Etching of Nanoporous Materials

Technology Transfer: This is proving out to be a fundamental research work now that we are diving into the ULK regimes for BEOL dielectrics. Data is being gathered directly on films used currently at TI and it ties in very nicely with our internal development work.

Impact statement: This work is giving us more in depth analysis of low k damage and restoration that we are seeing with ULK and subsequent porous films. We see this area as one of the key enablers to impact overall RC delay program requirements.

Research details: Prof. T.S. Kuan, U. at Albany

Impact statement: Assessment and understanding of fine Cu lines and the impact of scaling on Cu resistivity, a major issue for current and future technology nodes

Research details: Prof. Joost Vlassak, Harvard Univ

Impact statement: Fundamental studies and characterization of ULK dielectric reliability

Research details: Prof. Alan West, Columbia Univ.

Impact statement: Development of methodologies for the development and analysis of direct-on-barrier Cu metallization processes enabling improved process margin and Cu line resistance for interconnects

Research details: Prof. Azad Naeemi, Georgia Institute of Technology

Impact statement: Modeling of the physical limits for alternative interconnect structures, including non-conventional scaling and novel materials such as carbon nanotubes. Enables risk/performance assessments for these alternatives.

Research details: Prof. Carl Thompson, MIT

Impact statement: Fundamental studies and characterization of the structural integrity and reliability of Cu/Low-k structures

Research details: Prof. Ozturk, NCSU, Recessed Si(1-x)Ge(x) and Si(1-x)C(x) Source/Drain Engineering for Future CMOS Technologies Employing Uniaxial Channel Stress for Channel Mobility Enhancement

Impact statement: This program enables Professor Ozturk to continue his long record of contributions to the industry in recessed strained film materials and processes. This technology, which he pioneered in 616.009 by the development of strained recessed SiGe, is expected to provide key contributions to PMOS device performance through the 22 nm node. The natural extension of this work to recessed Si:C will enable NMOS performance enhancement.

Research details: Thompson, U Florida, Extending Strain Enhancements to the 22 nm Node for Si and/or SiGe Channels

Impact statement: Fundamental piezoresistance coefficients will be extracted at low and high strain and scaling issues with extending to the 22nm node will be studied. Experiments will use resistors, capacitors, and both long and short channel MOSFETs.

Research details: Seidman, Northwestern U, High Spatial Resolution/High Precision Characterization of Doping, Defectivity and Work Function Utilizing Kelvin-Probe Force-Microscopy (KPFM) and Atom-Probe Tomography (APT)

Impact statement: Three-dimensional composition profiling, with single-atom sensitivity and sub-nm resolution, of ultrashallow junctions, extensions, contact silicides, and high-K dielectric metal-gate stacks — all enablers to continued CMOS performance enhancements over the next 2-3 technology nodes.

Research details: Garfunkel, Rutgers U., Film and Interface Characterization of Gate Materials for Future CMOS

Impact statement: The primary objective of this research is to determine, with high spatial resolution, the composition, structure and thermal stability of gate stacks on strained silicon cheannels with a focus on the interfaces. These results will be directly correlated with studies of gate stack electrical properties and electronic structure. This program allows continued fundamental characterization studies of new gate stack materials. High-k / metal gate stacks are widely considered enabling technology for continuing Si-based CMOS performance trends.

Research details: Prof. Farhang Shadman, U. Arizona

Impact statement: Understanding the ESH and technical issues associated with new process and materials technologies

Research details: Gottlieb Oehrlein Univ. of Maryland

Impact statement: There has been a lot of progress made on this program. Prof. Oehrlein's group has submitted a number of conference presentations and technical papers on porous low-k etching/ashing, ULK damage and 193nm resist erosion. Their work has helped us in understanding the mechanism of ULK damage and 193nm resist etching during 45nm node etch/ash process development.

Research details: Application of Atomistic Models to Process TCAD for Nanoscale CMOS

Impact statement: Excellent progress was made during this project to calculate the impact of stress on various diffusion/activation processes. Due to extremely complex interactions, this is difficult to monitor experimentally. The group was able to find the important effects of strain (e.g. diffusivity stress tensor) for all the key dopants & point defects using theoretical modeling methods. A part of the project goal was to understand key co-doping & SiGe impact for which fundamental understanding and physical models have been lacking. The project has done a great job in isolating some of these mechanisms. For e.g they identified (using ab initio methods) the key physics that result in difference in doping profiles in SiGe Vs Si.

Research details: Prof. Choong-Un Kim, U. Texas at Arlington

Technology Transfer: Successfully expanded the voltammetry method to the evaluation of dielectric etch stop and pore stability in ULK as well as metal barrier integrity.

Impact statement: Development of characterization techniques for, and investigations of, the structural and chemical stability of diffusion barriers for Cu/Low-k interconnects.

Research details: Prof. Oliver Chyan, U. North Texas

Impact statement: Fundamental investigations of corrosion induced during CMP and cleans of Cu interconnects, including guidelines to avoid corrosion during interconnect processing

Research details: Prof. Oliver Chyan Univ. of North Texas Elimination of Bimetallic Corrosion at Dissimilar Metal Interfaces in Next Generation Cu Interconnect Microstructure

Impact statement: Work has provided extremely useful information on critical pH and oxidant regimes where bimetallic corrosion can be turned on or off. Has proven useful to C014 and expected to prove useful to C010. Would like to see funding continue for his work in this area with potential addition of supporting work on Cu ECD on Ru which is another area of expertise for his group. Students from this group are currently working at LAM and Novellus in the areas of cleans and ECD; this will help transfer the technology.

Research details: Prof. Rob Daasch, Portland State Univ.

Technology Transfer: We are actively working to deploy a statistical outlier program that co-developed through this SRC Custom program. We hired a student from this program.

Impact statement: We expect great savings by being able to move to partial burn-in on some products.

Research details: Prof. Mohammad Tehranipoor University of Maryland, Baltimore County (UMBC) — recently moved to U of Connecticut.

Technology Transfer: Test cost has been a growing concern, which has prompted the use of low cost testers and multisite testing. This research evaluates the use of low-cost testers for scan-based delay testing using techniques like on-chip generation of scan. A paper based on this research won the best paper award at VTS 2006.

Impact statement: The focus of this project is on delay fault testing using low-cost testers, which is of direct relevance to TI from the view point of saving test cost.

Research details: Ostling, Royal Institute of Technology (KTH), Pattern Dependency of Selective Epitaxy of SiGe-based Materials Grown by RPCVD

Impact statement: This research is providing modeling and understanding of the pattern dependency of selective epitaxial SiGe deposition. This is critical for this technology to be applied across a broad range of device designs at the 45 nm, 32 nm, and 22 nm nodes.

Research details: Prof. Jeff Kelber, Univ. of North Texas

Technology Transfer: Thin ALD barriers are a likely to be assessed for C010 and beyond. This work provides a fundamental insight into the evolution the interface between the barrier and OSG as well as between the components in a multi-stack barrier. The role of the various interfaces in critical for successful integration of ultra-thin barriers. Future work includes exploring ways to form sharp ALD/OSG interfaces, and should provide valuable data for 32nm node development.

Impact statement: Fundamental studies of interfacial chemistry and adhesion of ultra-thin, electroplatable diffusion barriers for advanced Cu/Low-k interconnects.

Research details: Prof. Paul Ho, Univ. Texas at Austin

Impact statement: Fundamental studies and characterization of the structural integrity and reliability of Cu/Low-k structures

Research details: Prof. William Eisenstadt University of Florida In-Situ Characterization of High-Speed Digital and RF Interconnect-Chip-Package Systems

Technology Transfer: Expected

Impact statement: This project will develop high speed (~ 10 Gbps) test chip designs for electrical model validation for very high performance products planned in the future. Future modeling software will be required to address high speed phenomena such as radiation effects, time retardation, and dispersion accurately and be able to handle multiple transmission modes. Insuring accuracy will require an efficient measurement capability with real devices at these high speeds. This program will provide the basis for this capability.

Research details: Zhigang Suo, Harvard University

Technology Transfer: Expected

Impact statement: Cracking of low-k BEOL and electromigration-induced damage are major reliability concerns. Although the industry produces tons of fracture test and EM test data, the explanations to those data are not conclusive and sometimes controversial. There is an urgent need for the basic understanding of the phenomena from the fundamental theory. An example is that the EM phenomenon in Al(Cu)/Oxide structure was well-explained by a 1-dimensional Korhonen model in the early 90's(Korhonen, Boergesen, Tu, Li, J. Appl. Phys. 73, 3790 (1993)). In the Cu/low-k era, models of low-k fracture and Cu EM are needed. Prof. Suo's pioneer work in interfacial fracture mechanics and electromigration modeling will definitely help the industry to gain some fundamental understanding of mechanisms of low-k fracture and EM failure.

Research details: Prof. Andreas Cangellaris University of Illinois Hierarchical Electromagnetic and Multi-Physics Modeling for Multi-Functional System-in-Package IC Designs

Technology Transfer: Expected

Impact statement: Exploiting package/chip co-design issues will become critical to guarantee product success in an efficient design process. This program will provide part of the solution for our industry by assessing signal integrity in a multi-physics environment as we expect new materials will be required for efficient transfer and shielding of signals at higher speeds.

Research details: 1393.001: Physico-Mechanical Properties of Intermetallics in Modern Solder Interconnects, principal investigator Dr. Morris Fine, Northwestern University, start date Feb 2006, and 1393.002: Modeling the Mechanical Properties of Intermetallic/Solder Interfaces, principal investigator Dr. Leon Keer, Northwestern University, start date Feb. 2006.

Technology Transfer: Expected

Impact statement: Many thermomechanical models and measurements have been made of Sn-containing solder alloys, yet few take into account numerical values for the assumed brittleness of the intermetallic compounds (IMC). This is because few numerical values for the properties such as fracture toughness, Young's modulus, elongation and tensile strength of the various IMC's formed between Sn and solderable metals such as Cu and Ni have been measured. The approach of these contracts- generating elastic constants from theoretical calculations, modeling the expected behavior, and then conducting measurements to validate the model - has an excellent chance to succeed. This will provide the data required for accurate finite-element models to describe the behavior of our packages' solder interconnections to our customers. Close interaction with the researchers, especially in choosing the appropriate measurement techniques, will be important.

Research details: Demkov, U Texas-Austin, Materials Development for Low-Resistance Contacts: Low-Schottky-Barrier Alloys

Technology Transfer: Expected

Impact statement: The main objective of this research is to guide the experimental development of new low barrier alloys for source/drain contacts in ultra-scaled CMOS.

Research details: Mohammad Tehranipoor University of Connecticut (formerly at University of Maryland, Baltimore County)

Technology Transfer: Expected

Impact statement: The work done by Mohammad Tehranipoor and his students has focused on the problems faced in the industry. Their work on test mode power dissipation, power-aware ATPG and small delay defects will be directly beneficial to our member company. If successful, we will be using them on our designs directly. Moreover, Dr. Tehranipoor's work most often uses commercial tools, and this makes it easier for us to directly apply the lessons learned.