2007 GRC Compelling Research Reasons

Research details: Automatic gate sizing and swapping algorithms are critical for leakage power minimization.

Technology Transfer: Murari Mani from Prof. Orshansky's group has been working with AMD over the last year to "productize" his algorithms for leakage power minimization in the presence of variability. The tool has been exercised on a number of 65nm and 45nm designs.

Impact statement: Murari's technique incorporates process variability into leakage power optimization techniques. This is expected to be critical for 45nm technologies and beyond.

Research details: Optimal placement of gates in custom design is critical to reducing power and meeting strict critical path requirements.

Technology Transfer: Tao Luo has worked within AMD as a co-op to help integrate his placement and gate sizing optimization techniques into AMD flows and validating the algorithms on our production data.

Impact statement: Automatic optimization of placement and sizing for full-custom blocks will help reduce power and/or increase performance without requiring as much designer intervention.

Research details: Quantify and model mechanical properties of BEOL structures to allow packaging into complex stacked and 3-D structures. Develop techniques and models to characterize chip/package interactions and assess strength characteristics of BEOL structures.

Technology Transfer: Transferred methodologies for improved adhesion and fatigue testing, dieseal/crackstop characterization and new understanding of materials interface issues for complex chip-package interactions.

Impact statement: Provides additional characterization methodology for interface engineering and good understanding of current chip-package mechanical reliability issues through collaboration with many member companies.

Research details: Low power Rx passive adaptive equalizatusing LC filter and frequency domain power analysis to drive adaptation.

Technology Transfer: Triggered the development of a new generation of passive Rx equalizers.

Impact statement: Low power receiver equalization for high speed links, expected to become very important as we drive beyond 8Gb/s in commodity components.

Research details: 425.021 Low-Water and Low-Energy Rinsing and Drying of Patterned Wafers, Nano-Structures, and New Materials Surfaces The proposed research consists of three subtasks: The first subtask focuses on the application of the novel Electro-Chemical Residue Sensing concept (developed at the ERC) to study the fundamentals of rinsing new surfaces and nano-structures - both of which present major ESH issues and challenges. This technology is a unique and promising method for in-situ and real-time measurement of residual contamination inside the micro-structures and microfeatures (the bottlenecks of cleaning, rinsing, and drying). A past ERC project has demonstrated the sensor's facility and sensitivity. The first subtask uses this technique to generate information on the kinetics and mechanism of rinse at a critical level that has not been studied or reported so far. In the second subtask, a combination of experimental measurements described in subtask 1 and the process mo

Technology Transfer: The ERC will commercialize this product by working directly with process equipment suppliers.

Impact statement: If this project is successful it could assist in meeting ITRS challenges for lowered water use, and could allow for shortened process times and increased throughput.

Research details: Wideband Frequency Synthesizer and Fast Hopping System Design

Technology Transfer: In consideration to improve SNR on high speed links, particularly using single ended signaling.

Impact statement: Increase the data bandwidth of low cost FR4 interconnects used in the commodity and consumer markets.

Research details: A series of three Cross-disciplinary Semiconductor Research tasks: 1276, 1375, and 1385 in which Prof. Michelle Simmons of U. New South Wales was principal investigator.

Technology Transfer: Through papers and presentations, Prof. Simmons has transferred new understanding of dopant behavior in silicon at an atomic scale and has provided insight into quantum-scale electrical behavior. Through her presentation at 2007 Techcon to GRC-funded students, Prof. Simmons has enhanced young (and some old) semiconductor engineers' interest in and enthusiasm for careers in our industry.

Impact statement: Professor Simmons' lab has unequalled capability to control the position and number of individual dopant atoms in silicon. She achieves this via scanning probe techniques, coupled with advanced methods of surface preparation and doping. Because of this atomic-scale control, she can observe electrical behavior at a resolution beyond current or even near-future industrial capability. She effectively employs modelling methods to support her experimental program and has turned the simulation results into movies to better convey her research findings. Prof. Simmons has demonstrated atomic level understanding of dopant incorporation (phosphorus) in silicon nanowires. She has demonstrated ohmic conduction in individually contacted silicon nanowires as narrow as 8nm. She has literally created a transistor with a scanning probe microscope.

Research details: 1437, shown above, is the current task. This submission addresses the Kummel-directed work that is part of NCRC (within 1437.003), and also covers 1136, a completed task.

Technology Transfer: Prof. Kummel provided an e-workshop (March, 2007) on Atomistic Models of Passive Oxide-Ge Interfaces. I believe there was also an e-workshop which provided a tutorial on the DFT computational methodology, perhaps in 2004.

Impact statement: Professor Kummel and his students effectively use a combination of modeling and experiment to gain understanding of semiconductor surface structure, electronic structure (density of states), semiconductor band-gaps, and chemical bonding of oxygen or metal oxide dielectrics to semiconductor surfaces. This has led to a more complete understanding of surface Fermi-level "pinning" and will be of guidance to industrial researchers seeking to minimize inversion thickness in mosfets with high-k dielectrics while retaining optimal carrier transport properties. In currently funded research, Professor Kummel's group is extending their work to surfaces of III-V materials being explored in the NCRC. Their modeling has provided intriguing new information about the InAs (100) surface structure. The influence of Hf (since the high-k dielectric could be HfO2) is also being studied experimentally and computationally.

Research details: Integration of two-dimensional thin carbon "substates" or graphene in the channel region of CMOS MOSFET's to get higher mobility and ultra-high performance.

Technology Transfer: The research looks at the next level of device performance beyond the mobility achieved by stressors in the conventional MOSFETs. It is far fetched right now, but it will help understand the challenges that lie ahead.

Impact statement: This should become important in the next 2-3 years as the device dimensions shrink and the industry is looking for ways to further improve performance.

Research details: Physical Synthesis for Power Under Process Variation

Technology Transfer: This research is still in its early stage. It investigates multi level and multi scale algorithms for physical synthesis under process variation. Finally it will create a framework for placement-driven optimization with multiple Vdd and Vth, cell sizing, Leff and tox

Impact statement: In the future it might become critical for the physical synthesis flow to target power optimization under uncertainty. This research will position us for that methodology.

Research details: Timing-Aware ATPGs for Maximizing Crosstalk/Signal Integrity Effects on SoCs

Technology Transfer: Dr. Mohammad Tehranipoor presented this work to the test community within AMD to give us exposure on the latest research that is being done for Signal integrity issues during test.

Impact statement: AMD currently uses commercial tools, so this research can benifit AMD only once the proposed techniques can be integrated with AMDs commercial tool flow. There is interest; further collaboration may result in work that can be done to adapt the proposed methods with our current flow.

Research details: Test-Pattern Modeling with Applications to Test-Set Selection, Test Generation, and Logic BIST University

Technology Transfer: Mahmut Yilmaz is working within AMD as a co-op in the ATPG team.

Impact statement: The results seen so far on benchmark circuits are promising. We have plans to validate Mahmut's proposed methods on AMD netlists and use to them for better pattern selection.

Research details: Silicon-based sub-25nm MOSFET's with graphene as channel material. The integration of such ultra-high mobility channel material may enable MOSFET performance better than that predicted by the ITRS.

Technology Transfer: This research just started 1 year ago, and a review was held at AMAT in March, 2007. Several liaison personnel from AMAT are engaged, and results of sophisticated modeling/simulation of some device structures indicated that graphene-on-FDSOI had the best performance. Another review at AMAT is scheduled for early 2008.

Impact statement: If successful, this channel material could enable superior performance of MOSFET's with simple processing. It also has the promise of being compatible with existing IC technology.....both in material interactions and processing tools. And it gets around the issue of having to precisely place CNT's in a MOSFET structure, as the graphene channel film is intended to be formed in a self-aligned process.

Technology Transfer: Introducing new circuit techniques extends the use of analog EDA tools, of great importance to Cadence's analog suite of tools. Cadence's Design Services does contract design on Analog, Mixed Signal & RF and the preparation of design kits to accompany these tools. Three areas of CDADIC research are particularly important: Data Converters—DACs & ADCs, Frequency Generators—Oscillators & PLLs, and ESD and Reliability structures

Impact statement: Over a number of years, the Analog/Mixed Signal design techniques developed under the CDADIC program have been critical to Cadence's success in designing these circuits.

Technology Transfer: Cadence provides design services to customers in the most difficult design areas. ESD protection of the highest speed circuits has not been properly addressed by industry. Her research is particularly useful in getting the high speed of the process realized in the chip's I/Os.

Impact statement: (This project was incorrectly entered in 2006 as ID 1366 rather than 1066). Tools to design I/O pads resistant to ESD but also applicable to high speed connections are urgently needed.

Technology Transfer: Both in IC chip design and in the design of packages and boards, accurate, efficient models of interconnects are essential. Cadence's EDA tools in both these areas benefit from this leading research in computationally-efficient modeling of interconnects over wide frequency ranges.

Impact statement: Although this project was completed in 2006, it is of continuing importance both to chip design and package/board design Cadence tools - we communicate with Prof. White regularly in this and allied areas.

Technology Transfer: Cadence's custom circuit design group uses the results of this research extensively in reducing the noise effects on sensitive circuits due to substrate noise coupling.

Impact statement: Cadence has made continual use of these developments in its custom circuit design business

Technology Transfer: Harjani's developments in rf circuit design are put to use in Cadence's custom design of state-of-the-art rf circuits.

Impact statement: Cadence has made continual use of these developments in its custom circuit design business.

Technology Transfer: Cheng's past work in this area has been very important in enhancing Cadence's Verification products. Tim Cheng maintains arguably the top open ATPG engine, this has proved very useful to Cadence for benchmarking

Impact statement: Current and past research is this area has been very important

Technology Transfer: Cadence uses CUDD and VIS in our formal analysis tool (IFV), developed under the previous project 920.001. The current project, 1365.001 promises equally important developments.

Impact statement: This research, over several years, has provided significant help in enhancing Cadence's Formal Verification tools, and is expected to provide important additional insights.

Technology Transfer: Clarke has been the leader for many years in development of theory and algorithms in Formal Verification, including the prior 1027.001 project of the same name. This project continues that important work to Cadence

Impact statement: Very important to Formal Verification

Technology Transfer: Has been very helpful in equipping Cadence's Analog Simulation product SPECTRE to meet the difficult challenges of simulation Oscillators and PLLs.

Impact statement: Significant value in enhancing Cadence products.

Technology Transfer: Achieving good performance of analog circuits such as PLLs is challenging at low supply voltages and increasing process variations. This project and CDADIC projects under #933 provide Cadence's custom circuit design group valuable help in meeting these challenges

Impact statement: Cadence has made continual use of these developments in its custom circuit design business

Technology Transfer: Cadence is investigation the potential of the software MFIPWA (Modified Fast Inhomogeneous Plane-Wave Algorithm) for enhancing the EDA tools for the design of ICs, Packages and Advanced Printed Circuit Boards as they are used to minimize crosstalk.

Impact statement: This project, which finished last year, has potential to improve Cadence's EDA tools for the minimization of crosstalk. We are investigating its applicability

Technology Transfer: Placement algorithms are an important part of several Cadence EDA products.

Impact statement: Has potential for speeding up some Placement EDA tools, which benefits both Cadence and the IC industry.

Technology Transfer: Potential for attacking difficult hardware/software co-verification problems

Impact statement: HW/SW co-verification technology evolves very slowly, this project has potential for moving this technology along.

Technology Transfer: Could significantly enhance ATPG EDA tools in developing efficient test patterns

Impact statement: Significant potential for attacking difficult Verification and Test Generation issues

Technology Transfer: The constraints imposed by sub-wavelength imaging cannot all be handled in mask fabrication, but must be addressed further up the design chain. This project introduces into the routing process these constraints.

Impact statement: Less costly mask fabrication and closer match between as-designed and on-chip interconnect patterns can result

Technology Transfer: Neureuther's past research, such as the California MICRO project "Feature Level Compensation & Control" have been productive to Cadence and provided a good start for this GRC project. This project may give key insights into how to couple EDA design tools to DFM requirements.

Impact statement: he research is forward looking and promises to significantly enhance Cadence' s EDA products n the future.

Technology Transfer: This has high potential in enhancing Synthesis and Verification technology

Impact statement: High potential

Technology Transfer: The development of testing and analysis methodology of drop/shock reliability experiments, using high speed video, digital image correlation, and leading indicators of failure, has the potential to introduce new reliability test methodologies that will be a great improvement over existing drop tests.

Impact statement: The development of leading indicators of damage during drop/shock stress should lead to better predictive reliability models. This is especially critical for advanced packaging solutions for handheld applications, which should become of critical interest to all member companies.

Impact statement: This project pushes the envelope of high efficiency RF PA design and realization. We have learned a great deal about our various technologies already in a very short time, have emulated their test system in order to be able to better transfer knowledge, and are able to focus on the more profitable lines of study. The interaction with UCSD has been very beneficial.

Research details: several CDADIC projects - In particular, Twisted Inductors with Low Coupling for Mixed-Signal/RF ICs

Technology Transfer: Our suggestions have been pursued with vigor, and we are kept well up to date on the structure of the inductors, measured results of experimental ICs, and proposals for future experiments.

Impact statement: SRC participation in CDADIC has strengthened an important analog center through direct funding of projects. In this project, first experimental ICs utilizing the twisted inductor technique show a 30dB improvement in isolation between closely spaced inductors. This is an enabling tactic for higher density integration and simultaneous operation of integrated RF components such as VCO's, LNA's, and PA's.

Research details: Investigate effects of scaling and material processing on the reliability statistics and failure mechanisms for EM and SM of Cu/low k interconnects.

Technology Transfer: The results obtained at Prof. Paul S. Ho's research lab at UT Austin are being used for current technology applications at the C45 and C32 nodes. Among other items, this research task investigates the electromigration scaling behavior. The ITRS roadmap currently predicts line dimensions of about 60nm in the 2008 and beyond timeframe. The UT Austin lab, in collaboration with SEMATECH, has fabricated lines of this dimension already in 2005, and has tested these lines for EM reliability, with very encouraging results. One of the most important parameters in EM testing is the lognormal spread of the failure time distributions (sigma). The results obtained at the UT lab enable an extrapolation to future technology nodes, a very important task in setting maximum allowed current densities in very fine Cu interconnects. Furthermore, the scaling behavior of Ta-based barriers has been assessed, as well as the scaling behavior of via sizes.

Impact statement: The impact of the work done at UT is very significant. As shown in the past, Prof. Ho precisely identified the most important issues of future interconnect systems. The reliability scaling behavior for very fine lines needed to be assessed. This has been done through a very elaborate study using backfill processes. This way, the UT group was able to perform an excellent look-ahead for future process generations.

Research details: Multiscale Modeling of Dopant Profiles with Improved Defect-Dopant Dynamics Models. UT -Austin

Technology Transfer: Both Arsenic and small interstitial cluster models have been calibrated and are ready to use in commercial Synopsys process simulator. We have started to use calibration parameters and models developed as a result of this project in guiding technology developments.

Impact statement: There was very close collaboration with both PIs and technology transfer was greatly facilitated by attending group meetings at UT-Austin and summer intern from the group. In the future, the project will contribute greatly to building a global calibration that would be transferable to broad range of processing conditions. It's impact may be not limited to traditional CMOS process modeling. Detailed, atomistic-level understanding of the semiconductor-dielectric interfaces and dopant-defect dynamics at the interface and in strained materials will likely have profound impact on our ability to provide simulation support for future technologies beyond CMOS.

Technology Transfer: An intern enabled great progress in getting the research implemented in SystemC runtime verification software. We had very good feedback and interest from the design community. The project is the first to reason about SysyemC verification with concurrency in mind. The intern performed several experiments and more is planned to be performed. We would like to continue to bring software and test the applicability of the technology.

Impact statement: This research is the first to reason about SystemC verification with concurrency in mind. It is very important for the industry's strategic system level modeling and verification direction. With the advance of complex concurrency in SoCs and multi-cores, their modeling and verification becomes more challenging. This research greatly impacts our verification and debugging capabilities by enabling reasoning about system level designs and concurrency that is unique and state-of-the-art.

Technology Transfer: We are now characterizing and investing substantial training effort to more fully incorporate PSP, the new industry standard model, into our company. PSP-SOI is coming out and also promises to be of great value to Freescale and other companies. The PSP MOSVAR model, a CMC standard MOS varactor model, is also a major work of this program. Having a good standard MOS varactor model will significantly reduce our effort needed to support our models in various simulators. A summer intern from the group developed statistical modeling capability for PSP, and is still looking into correlation modeling, something that no one else has done well.

Impact statement: The PSP model is key to our modeling and simulation strategy. We are now releasing PSP models and it is the only model planned to be supported for high precision RF and analog modeling needs. We are getting more requests for PSP models, particularly for switched capacitor IC design, because of issues with existing (BSIM) models.

Technology Transfer: We are working to implement the oscillator macromodel for fast simulation of statistical variations into Freescale's in-house simulator, Mica.

Impact statement: This work will significantly speed up the simulation of the impacts of statistical process variations on different oscillators' performances significantly, and will more importantly provide insights on which process parameters will affect designs the most to designers.

Technology Transfer: A summer intern applied this research on Freescale designs. The tools were enhanced with automated Verilog-AMS generation from Spice simulations and verification coverage metrics.

Impact statement: This research greatly impacts AMS verification. Given that chips increasingly contain AMS circuits, it is crucial to have formal verification techniques that enable reasoning about all possible corner cases of a design behavior. This work generates an abstract model from Spice simulations and runs formal verification algorithms on abstract models. Although model generation is still not mature, experimental results are promising. This work also demonstrated that assertion based verification can be used for AMS circuits as well as digital circuits.

Impact statement: These "optimized" cavity packages for MEMs devices indicate good mechanical stability and survived a production molding process. The team has recently produced working MEMS resonators. This new integration methodology could potentially result in a low-cost, high-throughput packaging for MEMS devices, one of the larger issues preventing real commercialization of MEMs.

Impact statement: This project has the potential for a large impact in the efficiency of our designs. Specifically the greatest impact will be in improving our designs for power and greater speed with a strong potential that impact of reliability wearout will have a much less negative impact on the final performance of the product.

Technology Transfer: Low Cost on chip sensors can predict infant mortality in the field and the chip or software can take corrective action. These sensors can be designed based on a specific process.

Impact statement: Transistors are getting cheaper fast and cost of testing these transistors is not getting cheaper as fast. Therefore, adding transistors to increase self-test is becoming cheaper than traditional test (external test). This project can reduce reliability testing costs (i.e., burn in) significantly.

Research details: This project seeks to construct a formal and practical framework that bridges the gap between transaction level modeling and RTL implementation using a formalism called Rendezvous Finite State Machines (RFSM). The project will refine the theory, develop a framework for modeling using RFSMs, and study algorithms for RFSM-based behavioral synthesis and verification.

Impact statement: We hope to use the RFSM modeling technology in our internal modeling and verification tools. As RFSM models are formal and fully analyzable, this technology will enable pre-RTL design verification to a larger extent. It may also allow us to develop high-level models and then directly produce usable RTL via behavioral synthesis.

Research details: Parallelization of IBM MoM full-wave electromagnetic field solver, EMSurf. The work consisted of generating code to distribute matrix storage, matrix fill operations, and matrix inversion needed for solving very large product level problems. UIUC delivered to us code that they were able to test on our BG supercomputer in IBM Rochester. This then allowed the smooth integration of the new code into our own software.

Technology Transfer: Matrix operations for parallel, districuted memory supercomputer cluster that could be directly used in IBM solver. Paper is being submitted to EPEP'07 conference describing the work..

Impact statement: Based on this collaboration and direct mentoring of graduate student Andrew Hesford, we were able to reach what we consider a milestone both in IBM and in the industry. We ran product level problem with 47-58% efficieny for both strong and weak scaling on 1024 BlueGene cluster and up to 0.5M surface unknown problem. Such large problems have not been handled until today and this enhances the capability of building fail-safe, high-performance server systems.

Technology Transfer: Several reports, excellent contract reviews including student presentations, offline discussions.

Impact statement: Pb-free solders are more challenging to implement than previously recognized. Chawla's concept of rare earth additives to alter properties offer several potential imprvement to what are now major reliability concerns with this class of interconnect.

Research details: Continued as Task 1644.001 Improving the Effectiveness Multiple-Detect Test Sets

Technology Transfer: Initially CMU is providing test vectors that IBM will use in production -- later technology transfer will be test pattern generation methods.

Impact statement: IBM does not yet have enough data to quantify the Quality improvements from using these patterns/methods. (hopefully to be completed by around December of 2007)

Research details: Research ID: 1608 -- Stochastic Modeling of Device Test Input, Test Flow, and Test Response

Technology Transfer: Statistical models for outlier identification aimed at product quality improvement / Testing

Impact statement: PSU has developed statistical models that can identify outlier product using IDDQ and other test results. The next phase of the project is to estimate Quality improvement vs. yield loss -- this quantification will determine the real impact to IBM.

Research details: University of Utah Ganesh Gopalakrishnan

Technology Transfer: Graduate student Xiaofang Chen is a summer intern at IBM T.J. Watson Research Center, 2007.

Impact statement: Through the SRC project with Prof. Gopalakrishanan, we are exploring methods for designing hardware protocols at a higher level of abstraction and formally verifying that the hardware implementations meet their high level specifications. These technologies are critical for IBM's future development of multi-core systems.

Research details: Project "VOSS" from University of British Columbia, formal verification for floating point circuits

Technology Transfer: VOSS was transfered to Intel with the hire of the student.

Impact statement: The technology eventually developed into Intel's leading formal verification tool "Forte" and became the framework for all of our formal equivalence verification. Today every FP design at Intel is verified with Forte-based FV.

Technology Transfer: Ober's work as usual is very high quality. Molecular glass resists are now showing up in supplier formulations that are being screened at Intel for EUV lithography. Ober's pioneering work has paved the path in these very novel resist platforms.

Impact statement: The impact of this work is very significant and immediate. As expected, these materials will take a long time to mature to the point of being useful in a production setting, but a solid understanding of the fundamental mechanisms of how the resist works will streamline the development efforts.

Research details: This seems fairly comprehensive. The idea of taking the models and embedding them in the PD design flow is excellent

Technology Transfer: Models and flow insertion points for comprehending the manufacturing effects pre-silicon.

Impact statement: Could have an effect on reducing the number of iterations to converge to a design solution.

Research details: Research on improve test quality from U of Iowa for the last 10 years.

Technology Transfer: Multiple algorithms and test methods have been delivered and tested out within Intel for the last 3 funding cycles from Prof Reddy's team at Iowa U, improving on the state of the art test practice. Collectively they helped improving test content coverage and lower test time (cost)

Impact statement: collectively improved test coverage for our processors without increasing test cost (time and footprint). The focus on test quality within given cost constraint is increasing due to the fact that design and validation cost did not scale (up) with technology. The impact of this line of job is even higher looking forward.

Research details: Non-PFOS/non-PFAS Photoacid Generators: Environmentally Friendly Candidates for Next Generation Lithography

Technology Transfer: Ober's work is the research trendsetter for getting a suite of candidate non-PFOS/PFAS PAGS characterized. These type of materials are critical for existing as well as future lithography needs should the class of materials fall under regulatory bans.

Impact statement: The global semiconductor industry has agreed through the World Semiconductor Council to eliminate the non-critical use of PFOS and analogs and work toward finding and developing alternatives for critical uses such as PAGs in photolithography. The agreement forms underpinnings of agreements at national (US, EU) and state level to continue use while substitutes are developed. This research is the key program to meet that expectation.

Research details: Destruction of Perfluoroalkyl Surfactants (PFAS) in Semiconductor Process Waters using Boron Doped Diamond Film Electrodes

Technology Transfer: This is groundbreaking research on the destruction in wastewater of a class of materials (PFAS) which remain a critical component in photolithography. This particular research has a novel and promising approach that potentially leads to a practicable solution to the waste discharge problem.

Impact statement: The global semiconductor industry has won acceptance with a variety of government authorities to continue use of critical applications (photolithography) for certain PFAS chemicals. The one identified area of remaining risk (basis for a full ban on use of the materials) is a dilute wasterwater release with no control. THis research is focused on mitigating that risk through development of novel and implementable treatment in water.

Research details: Profs. Diaz and Pan have made progress in applying principles of microwave characterization to package material characterization building a suite of tools that can be used by industry as we move to high speed busses.

Impact statement: The suite of tools being built can be used by industry as we move to high speed busses.

Technology Transfer: Prof. Muller continues to devise novel metrology methods for patterned films and interfaces. This year's contributions include electron tomography, Pixel Array Detectors and Valence Spectroscopy.

Impact statement: Expect that these novel techniques will provide new insights and enable developments in the areas of barrier/seed and microstructure evolution. Several other SRC tasks have benefited from analysis from Prof. Muller.

Impact statement: Prof. Nied has developed a comprehensive software suite, that has been transferred to Intel and is being used to study silicon package stress interactions as we continue to integrate new ILDs in our silicon processes

Research details: Simulation of electronic transport in "Unconventional" MOSFETs

Technology Transfer: This work is providing fundamental theoretical understanding of transport effects in III-V devices.

Impact statement: Provides insight into the scalability of non-silicon materials and their potential for replacing or complementing silicon devices at a future technology node.

Technology Transfer: The project started late relative to it's ideal "need" date. That said, it is useful and relevant to the industry, especially with with the new focus on LPP for higher power EUV tools. Rather than be transferred to Intel, the results of this project need to be transferred to the EUV source manufacturers (LPP supplier specifically) and tool suppliers to be most beneficial to the industry.

Impact statement: The impact of this work could be recognized as soon as the PI gets an audience with the source and tool suppliers.

Impact statement: Prof. Chawla has made significant progress in identifying and characterizing RE doped, Pb-free solders that offer potentially new opportunities for shock resistant applications in handheld and mobile devices.

Research details: Interface Characterization of Novel Channel and Gate Materials for Future CMOS

Technology Transfer: Prof Garfunkel always provide availability to characterize new materials/channels to help to understand critical roadblocks of implementing technologies such as high k, Ge and IIIV

Impact statement: important metrology methods to characterize new channel materials and scaled device structure

Research details: Droplet on demand has signficant potential for chip packaging application as the bonding strength & conductivity is hugeley improved over conventional soldering techniques

Technology Transfer: Intel packaging group in Chandker (AZ) is actively engagement and interested in the research.

Impact statement: Feasibility of DoD is being evaluated

Research details: BCP directed self-assembly has potential to pattern subresolution features to overcome optical lithography resolution limitations.

Technology Transfer: Intel has hired a summer intern to do grapheoexpitaxy in-house.

Impact statement: The research is just exploratory for the time being

Technology Transfer: Demonstrated novel techniques to experimentally identify the mechanisms of leakage and time dependent dielectric breakdown (TDDB) in low-k thin films.

Impact statement: These techniques will likely contribute to a more fundamental understanding of TDDB in novel interconnects.

Technology Transfer: Prof. West applied a microfluidic tool to conduct electrochemical characterizations to provide fundamental understanding of plating additives and their impacts on different substrates.

Impact statement: Prof. West's results can be applied to optimize seedless direct plating processes, from the initial nucleation to the final gap-fill stages, and design of novel additives.

Technology Transfer: Intel has tested SNFUH for several applications. The technique is solid, but more modeling is needed. We expect that this will be a great metrology addition to an AFM tool in the future.

Impact statement: Not much university work is focused on metrology, and this is one project that richly serves the need of detecting small defects nondestructively. The main value of the work will come once prototype tools are available, but the need is NOW!

Technology Transfer: DSA is still in the external research phase, but is being investigated by Intel. We did have a summer intern from Nealey's group at Intel last summer to do a project on DSA, and will continue the collaboration in the future.

Impact statement: As CDs shrink, traditional resist materials will likely not scale and new ideas such as self assembled materials will be needed. Such breakthrough ideas are perfect opportunities for universities and students to engage to meet the future needs of industry.

Research details: Spin-Torque-Switched MRAM Devices and Circuits

Technology Transfer: Novel materials and MRAM characterization techniques, important for transfer know-how to company member to evaluate such new memory technologies

Impact statement: critical new memory research that will lead to potential scaled RAM device cell , for 22 nm node and beyond

Technology Transfer: research results and materials will be useful for companies to develop IIIV prototype device for 22 nm node CMOS

Impact statement: critical to identify IIIV CMOS transistor for 22 nm node

Impact statement: Prof. Franzon offers a high risk but potentially high reward solution for future bandwidth demand. His solution strategy if successful could help contain pin count increases concomitant with increased bandwidth demand and differential signaling.

Research details: This project focuses on new types of devices (FIN FETs). Specifically they are looking at new logic faimilies based upon this technology.

Technology Transfer: Could provide some interesting exploration results. After their research, it is likely that we would be able to narrow our solution search paths (if necessary).

Impact statement: Impact focus would be on logic families and standard cell topologies. Too early to quantify impact.

Technology Transfer: Identify/predict aging failures on filed

Impact statement: provide an alternative low cost solution to traditional burn in. Potentially the same technology can be leveraged to detect other kinds of failure in reliability schemes.

Technology Transfer: understanding of IIIV interface will be very useful to enable companies in development of IIIV MOS device for 22 nm

Impact statement: In-Situ Growth of Gate Dielectrics on III-V Channels is critical to understand passivation issues of IIIV surfaces.

Research details: investigate compression algorithms and associated hardware implementation issues related to maskless lithography data architecture; understand the inherent trade offs between complexity and compression efficiency for various layouts

Technology Transfer: none submitted

Impact statement: Produced workable compression algorithms for maskless lithography,and extended to produce a kind of "hybrid" approach to OPC. That may become critically necessary to enable maskless lithography.

Research details: Study the impact of lithographic and RET based variability on circuit performance and develop new methods to improve circuit performance in the presence of variability

Technology Transfer: Brian Cline did a summer internship pursuing his research with real life data at Mentor and provided quantitaive insight into the intrinsic value of lithography variations on elctrical circuit repsponses.

Impact statement: Thiis research shows that a litho-aware model is able to reduce the worst case absolute error in rise and fall delay considerably (several X) when compared with other approximations that are used routinely in SSTA methods. As SSTA methodologies start to take off, this research hints as the necessary work needed to characterize delay.

Research details: Performance-oriented parameter dimension reduction using reduced-rank regression for interconnect modeling. Fast quadratic stage timing model characterization and quadratic statistical static timing analysis

Technology Transfer: One of the students, Zhuo Feng has had a summer internship with Mentor on the subject of "performance oriented process corner characterization". This interaction translated into promising directions for solving practical industrial problems.

Impact statement: Prof Peng Li continue his research towards the general performance oriented statistical Process Variation corner analysis as well as fast spice simulation techniques (such as parallel computing) and current source model based cell characterization. We believe the industry will continuously benefit from his research work.

Research details: produce definitive experimental and theoretical results to evaluate directed assembly of block copolymers to extend lithographic processes and fabricate devices with critical dimensions below 10 nm, and we will explore potentially revolutionary new paradigms for defect free and registered fabrication of multi-component device oriented structures in three dimensions

Technology Transfer: none submitted

Impact statement: Progress has been made demonstrating the fabrication of 20-nm scale circuit-like features resembling dense lines, isolated lines, bent and curved lines, jogs, and dense contact holes and in reducing annealing times from days to minutes. Molecular modeling software tools have been created that may have application in modeling lithographic processes. The adoption of DSA materials represents a possibly inexpensive, "bottoms-up" paradigm to nanoscale patterning.

Research details: Develop a suite of optimization methods using a new optimization framework for process variation tolerance using variation space sampling for applications including V(th) selection, L(eff) biasing, gate sizing, and post fabrication tuning using ABB clustering

Technology Transfer: none submitted

Impact statement: This is a good opportunity to determine which other methods in addition to layout robustness can be used to achieve variation tolerant circuits, the current research requires to do a deterministic variation space sampling (similar to the completed task) and how such information can be used to adapt body bias to achieve lower leakage and tighter delay spreads.

Research details: Tailoring NiSi Chemistry for WNx ALD: Oxidation, Precleaning, and WN Precursor Interactions.

Technology Transfer: Research results on oxidization characterization on NiSi (with and without Pt) have provided good insight into the formation of different surface oxide layers.

Impact statement: The finding is useful in understanding the cleaning efficiency of the subsequent step prior to barrier/metal film deposition.

Research details: This is the work of Professor Alan West at Columbia on the development of methodologies for the analysis of direct metallization processes.

Technology Transfer: This program matches our internal interests in the electroplating area very well. Prof. West developed a simulation of the impact of nucleation density, resulting local sheet resistance, and the resulting plating distribution across a long resistive electrode associated with the terminal effect. The simulations were then used to compare the nucleation length to the resistivity behavior seen when plating on a thin film pt electrode.

Impact statement: This work has relevance to electroplating copper on ruthenium, and may be useful in interpreting the measured copper sheet resistance as a function of the volume of copper deposited and the shape and distribution of the copper nuclei as observed using SEM.

Research details: Extending Cu/low-k technology beyond 45nm will requires overcoming the so-called "size effect" in sub-50nm lines that has been shown to increase conductor resistivity far beyond that of bulk Cu which adversely impacts circuit latency, joule heating and reliability. Mitigating the size effect will require (1) reducing electron reflection at Cu grain boundaries, (2) increasing specular scattering at the Cu/barrier interface, and (3) developing interconnect architectures with reduced line length and/or increased line dimensions. The NY CAIST is addressing these issues, among many others.

Technology Transfer: Novellus continues to recognize the value of the NY CAIST as a one stop shop for interconnect research, which focuses primarily on the extension of copper low k technology. Transfer continues to be achieved via our assignee to the GRC at UAlbany-SUNY and by diligent mentoring of key programs.

Impact statement: (1) The pioneering experimental work of T. S. Kuan (most recently Task 1292.007) has quantified the role of different liners and barriers, both materials and methods (e.g. ALD, CVD, PVD) on the initial Cu seed layer and the final electrochemically deposited Cu line, (2) More recent work of Dunn and Lipshin (Task 1292.026) has already provided understanding of the growth of large Cu grains in fine features which may allow us to overcome the problem of reducing grain boundary scattering in narrow trenches, (3) Modeling work by Naeemi and Meindl (Task 1292.018) has opened the door to architectural solutions to the size effect by quantifying and optimizing overall circuit performance as a function of both wiring levels and wire size distribution, (4) Work by Gall (Task 1292.004) has shown, for the first time, that it may be possible to greatly increase specular scattering at the Cu-barrier interface by carefully controlling the atomic scale roughness.

Research details: This is the work of Professor David Graves at Berkeley. Plasma surface interactions with ultra-low k materials; investigation of ULK damage. The work uses a combination of process equipment and metrology.

Technology Transfer: This program matches our internal interests in the plasma/low k area very well. It leads nicely into understanding the interactions between the low k materials and beams of reactive atoms like oxygen, hydrogen and nitrogen or various beams of radicals such as Ar+, Xe+ and Oxygen. The results impact process development for the application of ULK materials; particularly their susceptibility to damage from etching or surface cleaning.

Impact statement: This work is on going although the potential significance of the work has been realized for some time. The work is incomplete but is generating valuable information, particularly the impact of oxygen on the low k films.

Research details: Etch studies of low-k materials.

Technology Transfer: Prof. Sawin has provided us with detailed and high quality etch and surface roughening studies on low-k material samples created at Novellus specifically for this research task.

Impact statement: These results demonstrate aspects of the low-k materials that might otherwise not be readily apparent.

Research details: World class modeling capability by Prof. Kushner and his students, that has been ongoing for many years, but which continues to provide improvements to our ability to model plasma processes.

Technology Transfer: Technology Transfer of HPEM, DTS, MCFPM codes are continuous at Novellus Systems. All the codes are used throughout the company through our centralized modeling group. Most of the code capabilities are not found in current commercial codes on the market. Prof. Kushner has recently focused significant effort on processes of direct Novellus interest, such as ionized PVD and HDP-CVD.

Impact statement: The research has been recognized previously and continues to provide significant value to Novellus Systems. The codes are heavily used at all phases of product development. Simulation results provide process insight that is not currently possible through ordinary experimental means.

Research details: Extension of copper technology to the "end of CMOS". There are multiple programs funded largely through the CAIST which bear on the extension of Copper interconnect technology. The professors names are Kuan, Gall, Dunn, Lifshin, Engstrom, Ekerdt, Muller and West.

Technology Transfer: This work impacts a large part of the semiconductor industry; in that at this time we do not have a conductor that can be used for on chip interconnect that is better than copper, and copper itself is being impacted adversely by the shrinking dimensions of the interconnect. This compendium of programs provides reasonably comprehensive coverage of the key areas for research; scaling; electron scattering; modeling; grain growth; processing, barrier materials, and metrology.

Impact statement: The work in these programs can help us extend copper to its ultimate limits. It is labeled for future impact because the work is recognized as being significant but the actual impact of the research is not yet on the table.

Research details: Tailoring NiSi Chemistry for WNx ALD: Oxidation, Precleaning, and WN Precursor Interactions, Jeff Kelber, University of North Texas.

Technology Transfer: This same task is also in the newly recognized category but for differnet reasons. Investigation of the interaction of the post NiSi clean surface with the ALD WN layer can provide useful knowledge of alternative chemical clean methods and barrier materials (ALD WN), which can directly impact the industry.

Impact statement: NiSi contacts are in widespread use in logic devices. As the device dimensions shrink, precleaning of NiSi at the bottom of the contacts using conventional sputtering technology becomes increasingly difficult. As an alternative a chemical clean is being developed. For this to work, a good understanding of the nature of the oxide is important. In addition, in an advanced contact fill scheme, where barriers such as ALD WN are used, it is important to understand the integration issues that one might encounter. With regard to integration, Prof. Kelber has recently determined that exposure of NiSi to atomic O forms a transition metal silicate on the surface -- Ni silicate or Pt silicate if (Pt)NiSi is used -- whereas exposure to molecular O2 results in an SiO2 surface layer which is easier to remove.

Research details: This research focuses on the development of plasma diagnostics that allow the measurement of the plasma in the volume above the wafer, with RF power applied to the pedestal.

Technology Transfer: These diagnostic tools have direct application to existing and developmental plasma tools, such as PVD and HDP-CVD systems at Novellus.

Impact statement: The work in this program will help us better understand how our process parameters affect the plasma, and then how the plasma conditions affect our films. It is labeled for future impact because the work is recognized as being significant but the actual impact of the research is not yet on the table.

Impact statement: This custom funded Task "BSIM Next Generation Model Research and Development: Surface-Potential-Plus," which was completed in Dec 2006, led to a follow-on project by our member company. This work led to a VLSI 2007 paper "BSIM-MG: A Versatile Multi-Gate FET Model for Mixed-Signal Design" that was selected as the best student (Mohan Dunga) paper at the conference. The resulting work provided our member company with a full-fledged, versatile, surface-potential based Multi-Gate FET (MuGFET) model with several novel modeling features. BSIM-MG has also been verified against experimental data demonstrating its applicability for mixed signal design.

Research details: Choong-Un Kim UT-Arlington

Impact statement: Work enabled reliability margin assessment of ultra-thin BEOL barriers in 65nm/45nm node interconnects

Research details: Oliver Chyan U. North Texas

Impact statement: Work enabled fundamental understanding of bimetallic corrosion behavior observed in manufacturing with different metals and CMP/cleaning agents.

Research details: Clock Network Synthesis for High Performance, Low Power and Reliable IC Designs

Technology Transfer: Our member company hired a student from this program.

Impact statement: Th research in design techniques to increase clock-tree robustness was very applicable to our member company needs. We hired a student from this program, and he is working on a design team implementing clock trees for high-performance designs. The standard technique to perform this work is to use Clock Tree Synthesis (CTS) tools provided by EDA vendors. In order to implement clock trees suitable for high-performance designs, CTS tools require a lot of guidance, detailed analysis of the results, and manual fixes. Due to his graduate school experience in EDA, this new employee realized that he could drive the CTS tools from one vendor via a standard optimization technique. Via this technique, on a real design, he demonstrated better results in a couple of days of run time than what were obtained by expert designers working for several staff months. The technique is currently being applied to several chip projects, simultaneously raising the quality of the cl

Research details: Kathlene L. Melde U. Arizona

Impact statement: Developed broadband material characterization techniques used by our member company packaging development group

Research details: T. S. Kuan U. Albany

Impact statement: Work enabled early definition of 45nm/32nm node interconnect design rules by determining and quantifying source of anomalous Cu resistivity at fine feature sizes.

Research details: Azad Naeemi Georgia Tech

Impact statement: Modeling of physical limits for alternative interconnect structures including carbon nanotubes, carbon ribbons/graphene, and non-conventional scaling approaches. Enabled risk and performance assessment of these materials and approaches for devices beyond the 32nm node.

Research details: Wooley (Stanford). Low-voltage, low-power digital-to-analog conversion.

Impact statement: Ongoing impact

Research details: Joost J. Vlassak Harvard U.

Impact statement: Enabled improved reliability of 65nm/45nm interconnects and device packages though comprehensive study of environmental and chemical effects on porous ULK dielectric fracture

Research details: Jeffry Kelber U. North Texas

Impact statement: Helped enable engineering tuning of ultra-thin metal barriers for 65nm/45nm interconnects through a detailed understanding of interfacial chemistry and reaction kinetics of interfaces with ULK films and thin barrier materials.

Research details: William R. Eisenstadt U. Florida

Impact statement: Developing I/O interface test ICs for in situ high-speed I/O test of chips, packages and board technologies of interest to member company packaging research group.

Research details: Paul Ho U. Texas at Austin

Impact statement: Developed a method to directly measure the grain boundary diffusivity and interface diffusivity of Cu using the stress relaxation experiment of Cu films. This is a major contribution to the industry. These data are crucial inputs for modeling electromigration and stress induced voiding.

Research details: Andreas C. Cangellaris Univ. of Illinois/Urbana-Champaign

Impact statement: Insightful Electromagnetic and physical modeling of Multi-Functional System-in-Package Designs using non-linear, transient simulation for member company packaging development

Research details: Profs. Gautam Ghosh and Leon M Keer Northwestern U.

Technology Transfer: This program establishes a method to calculate the IMC elastic constants, verify by experimental measurements, and model using these results to refine our current understanding of solder joint reliability.

Impact statement: It will lead to more reliable modeling and predictable lifetime results. Thermomechanical models are being used to attempt predictions of the useful life of solder connections in electronic packaging. While the stress fields that the models indicate are accepted, exact values of the useful life and accurate prediction of the failure mode is still lacking. For instance, many experts in the field refer to 'brittle solder IMC compounds' as a reason for failures in solder connections. However, most solder fatigue analyses find cracks in the solder near ??? but not at or in ??? the IMC region. Most modeling studies claim the lack of knowledge of the IMC's physical properties — elastic constants, thermal expansion, etc. — as a source of significant error in this part of the model.

Research details: Physico-Mechanical properties of Intermetallics in Modern Solder Interconnects

Impact statement: Elastic modulus and other properties of solder intermetallic compounds (IMC) are difficult to measure, therefore computer models of solder joints ignore the contributions from IMC's. This program calculates ranges of important IMC properties from theoretical models based on the IMC crystal structures, and performs measurements where possible to validate the calculations' results. Very useful for improving mechanical models, and providing our customers better information on using our products.

Research details: Prof. Madhavan Swaminathan Georgia Institute of Technology

Impact statement: Developed new EBG structures and power distribution networks methods for system in package structures.

Impact statement: This research explores a new optimization framework for process-variation tolerance using variation space sampling. The fundamental idea behind this research is the probability of worst- case scenarios is really small and the techniques exploit this fact to design for a typical/average case scenario. Our member company has used this approach to to explore various design margins and systematically removes the pessimistic performance margins. This saves both run-time and produces an area benefit for the circuits.

Research details: F. Shadman, University of Arizona

Technology Transfer: Our member company has hired a number of outstanding students from this ESH research center.

Impact statement: This research effort that puts focus on ESH impact of technology gives an outstanding perspective to the education of the students, and shows an SC industry commitment to ESH. This ESH research has specifically shown the industry to be proactive in ESH and has brought tremendous value in dealing with regulatory bodies across the world.

Research details: CDADIC Membership

Technology Transfer: Our member company has hired a recent graduate for one of our design groups.

Impact statement: Very good value for the funds. The work is also very good and because of the 1-year project nature; new topics can easily be investigated.

Research details: Alam and Roy, Purdue

Technology Transfer: Our member company has been able to hire out of this program, including a 2007 graduate who will join our member company.

Impact statement: Kaushik is a leader in the area of low-power design in leading edge processes and his graduates are very well trained to work in member companies. Mohamed is an expert in reliability effects (eg NBTI) and this work has received widespread recognition.

Research details: Rosenbaum and Shanbhag (UIUC). Highly Reliable Receiver Circuits for High-speed IO Links.

Impact statement: Ongoing impact

Research details: Yang (UCLA). Optimal Receiver for 20GBPS Serial I/O Links.

Impact statement: Ongoing impact

Research details: Pileggi (CMU). Circuit Primitives for regular logic bricks

Impact statement: Ongoing impact

Research details: Ken O, U. FL - Feasibility of implementing cmos rf front-end circuits for 76-77 ghz radar.

Impact statement: Ongoing impact

Technology Transfer: Prof. Cao has visited our member company and described his research and approaches for developing compact models for reliability degradation.

Impact statement: This project addresses issues with current reliability compact models and has generated alternative approaches that can address reliability degradation mechanisms in current and future deep sub-micron CMOS technologies.

Research details: Murmann (Stanford). System embedded calibration of a/d converters

Impact statement: Ongoing impact

Impact statement: Our member company has reached a major milestone in the form of a production release of the advanced statistical outlier system developed in conjunction with Prof. Daasch and his team at Portland State University. It is fully integrated with our member company manufacturing flows and is already being used successfully on several high volume products.

Impact statement: This work explores a new approach to compact reliability modeling that may complement and replace our current techniques. We have colloborated extensively with them and this joint work will be presented at upcoming conferences and in publications. We are also considering further colloboration with them in developing special test structures for comprehending circuit reliability effects.

Research details: Cao (ASU). Predictive modeling and simulation of reliability degradation in nanoscale circuits

Impact statement: Ongoing impact

Research details: Paul Nealey U. Wisconsin

Impact statement: The research on templated self assemply is outstanding and has led the field in templated self assembly. We expect this to have great impact to nanotechnology patterning approaches for the future.

Research details: Ganesh Subbarayan and Thomas Siegmund Purdue Univ. Nanoscale Characterization and Hierarchical Multiscale Modeling for Enhanced Cu/Low-k Reliability Analysis

Impact statement: This project develops a method to measure the adhesion of thin films with a sample preparation procedure "clean-room compatible". The project also develops a method to extract the adhesion parameters using the cohesive zone method. It has the potential to be adapted as part of the metrology for thin film adhesion measurement.

Research details: Modeling the Mechanical Properties of Intermetallic/Solder Interfaces

Impact statement: Models to take into account imperfections in solder joints, very useful since most models have a 'perfect-joint' appearance, yet we know real solder joints have nonsymmetric appearances. This reasearch also attempts to write a cohesive-zone subroutine for ABAQUS models, which will be very useful for fast, accurate modeling if successful.

Research details: Genesh Subbarayan Purdue University Valid Constitutive and Relevant Failure Models for SnAgCu Solder Alloys

Impact statement: This project will result in comprehensive rate-dependent viscoplastic constitutive models for SAC alloys that are valid for both quasi-static and high strain rate (shock load) conditions. The constitutive models in conjunction with the nonlinear fracture models will be used to predict fatigue life under accelerated testing conditions and under field use conditions.

Research details: Adaptive High Dynamic Range Equalizer and Automatic Skew Compensation for High-Speed Data Communications

Impact statement: Prof. Liu is investigating ways of equalization and skew compensation techniques over low cost transmission media. These techniques will be adaptive to allow for process and media variation. Although the research has just begun, the development is critical for next generation high-speed communication circuits.

Research details: Surface Kinetics of Dielectric Patterning and Contact Etching

Technology Transfer: A lot of what is understood in the industry about roughening and how to capture it in simulation is based on Sawin's current and past SRC work. Basically all silicon related "yield" data used in SRC company work finds its source in SRC sponsored work. TEL is now learning MIT's roughening model and will use it as an R&D tool to study roughening effects for new process technology development.

Impact statement: Sawin, in this funding phase, has shown how process integration can impact LER and LWR primarily through templating effects that are controlled by chemistry. Through modeling, he has shown how the details of the angle dependence of the yield curve determine the type of roughening that is observed. In addition, his new "mixed layer" model has the promise of simplifying the way plasma surface chemistry is captured in predictive feature scale models.

Research details: Plasma equipment process and feature scale modeling and simulation with the Hybrid Plasma Equipment Model HPEM

Technology Transfer: HPEM is now used at TEL. Many of the insights from Kushners work regarding electromagnetic effects in chambers, atomic layer etching, twisting in structures are relevant to state of art plasma tool development.

Impact statement: HPEM has become the state-of-the-art plasma process simulation tool in the semiconductor industry. His recent work on ALE, charge effects in deep structures, and electromagnetic effects in equipment complement our R&D activity.