The Center explores new concepts for the transistor to dramatically lower the power requirements for electronics. Today’s integrated circuits are limited by power dissipation. The mission of LEAST is to discover transistors that outperform CMOS at low voltage (less than 0.4 V).
The Center builds on research in steep device technology developed in the SRC Midwest Institute for Nanoelectronics Discovery (MIND). LEAST widens the search for physical mechanisms leading to abrupt transistor switching including the tunnel field-effect transistor and collective switching mechanisms associated with ferroelectric gates and phase change materials. The center has a strong focus on materials growth, modeling, characterization, and physical understanding . Device benchmarking, circuit development, including memory, and new system architectures are also under investigation to drive applications.
Theme 1: Materials, Interfaces, and Surfaces. This theme provides the materials understanding in the Center and focuses on fundamental challenges associated with growth, interface control, and surfaces for steep devices.
Theme 2: Quantum Engineered Steep Transistors. This theme is a device Theme aimed at understanding and demonstrating steep slope tunneling devices in 2D graphene and dichalcogenide crystals, III-Nitrides, and complex oxides.
Theme 3: Transduction Components. This theme explores transduction mechanisms beyond tunneling to further lower subthreshold swing and add new functionality to steep devices.
Theme 4: Benchmarks, Circuits and Architectures. This theme will provide the benchmarking activities in the Center and explore applications for steep technologies including low-power digital logic, low-power analog, high-frequency mixed signal, security, non-von-Neumann machines, and nonBoolean computing.
Last Year3 Research Publications4 Patent Applications2 Patents Granted
Since Inception4 Research Themes14 Universities218 Students50 Faculty Researchers45 Liaison Personnel1,409 Research Publications5 Patents Granted