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Researchers have built a physics-based STTRAM compact model consisting of four subcircuits, and used it for variability studies.
LMD Featured Publication: STT-MRAM Scaling and Variability Studies using an MTJ SPICE Model
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New envelop-following formulation gives runtime speedup of 30X over transient simulation for DC-DC converters.
CADT Featured Publication: Report on an Improved Envelope-Following Simulation Algorithm for Switched-Mode DC-DC Converters
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A new adaptive anti-counterfeiting technique generates unique IDs for digital chips using analog excitation and post-processing.
CADT Featured Publication: Final Report on Adaptive Test Strategies for Minimum Energy Electronics
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New post-silicon bug localization technique achieves four orders of magnitude improvement in test runtime.
CADT Featured Publication: Technical Report on Overall Infrastructure Combining Detection and Localization
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Fast power-on PLLs are critical for power proportional on/off high speed links. This design locks in 1ns, an improvement of 10X.
AMS-CSD Featured Publication: Report on the Complete Circuit Design and Chip Layout of the Optimized Clock Generator
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TECHCON 2015 Call for Abstracts - Deadline Extended
The deadline for TECHCON 2015 abstract submissions has been extended to 3:00 p.m. ET, March 2, 2015.
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GRC Remaps its Research Categories
SRC's longest-running research program has reorganized the technical categories by which it manages its research efforts. The science area designations have been eliminated and the 18 former thrusts have been mapped into 11 thrusts.
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SRC Professor Elected to the National Academy of Engineering
Gabor C. Temes, a distinguished professor emeritus of electrical engineering at UCLA, and currently a professor of electrical and computer engineering at Oregon State University working on SRC research was elected to the National Academy of Engineering.
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Researchers have demonstrated graphene growth on thin Cu film substrates down to 550 C.
NMS Featured Publication: Report on the Measurements, Analysis and Conclusion of Scalability, Conductivity and Reliability of the Cu/Graphene-hybrid Interconnect and Comparison with Standard Barrier/Cu Technology
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Re-use of BIST infrastructure to monitor and predict circuit aging has low area and power overhead while giving high accuracy.
ICSS Featured Publication: Re-using BIST for Circuit Aging Monitoring
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A novel low power real-time image processing architecture has been developed that uses 18% less memory than other implementations.
ICSS Featured Publication: Wireless Baseband SoC RTL0 Description (Surveillance Derivative)
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Generalized contact self-energy method has been augmented in NEMO5 to include phonons to simulate heat transport.
DS Featured Publication: Report on the Assessment of Silicon-free Transport in Realistic Nanoscale Devices with NEMO5
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New analog/mixed-signal test technique shows 40% reduction in test time without loss of coverage.
CADTS Featured Publication: Report on the Demonstration of the Proposed Fault Coverage Analysis Method on Representative Analog/Mixed Signal Circuits
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New multilayer defect tolerance methodology improves performance-per-area by 2.6x at the 8nm node.
CADTS Featured Publication: Projecting the Efficiency of Our Cross-Layered Defect-Tolerance Approaches for Multicore Processors
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Desorption studies of Hf and Sn based EUV resists shed new insight into their thin film composition and patterning mechanism(s).
NMS Featured Publication: Report on Incorporating High Photo-absorption Coefficient Elements into Inorganic Resist
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